From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CBF410D37; Fri, 10 Jul 2026 10:52:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783680724; cv=none; b=c6MWI3iwuiTwWIBAFsMjHK8CmUSjtXYr0d63iZRhMoHKLDS+phbWoB25R6UqaWYCsvf9t8k0roymzWAxuXeKlB34EJgRBBGbl+YarEl6W7+rDy8JZMDL+2gJsNkg5uHUSvPtPHDAxZW3pXM6B1uTeyqUdTgY2PcYTZOsMZ+k5VI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783680724; c=relaxed/simple; bh=Eh8Jr/bt1zOt2HZr7M1nIEJDT7mOtZL5uRRxBHnXp08=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=CiHp7HzCgtgLcb991B66mRvwLR5IGpW7x87oxbqvV803aXKiQNOtzmWAgAhl1QTQ3UUequBvPgdQG92YZraarVIbKwVsqc/9I6mICUIiznXh6JdBQlOrsQd2ADALOCwA9pENBfjWSOj1EvbdWzXYbwmhrtvwZAxLrdz1R9ZW4ws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L22NAzx0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L22NAzx0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1FA51F000E9; Fri, 10 Jul 2026 10:51:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783680722; bh=BaH7g5yuPZ2RiR84qm+ckDuciPNtOqn5l+saj85/HzM=; h=Date:Subject:From:To:Cc:References:In-Reply-To; b=L22NAzx0fKerAZ8K4VJbMUiT9bJM/fAygqwS/NbAzL+lB4nTb98q4lLfzUMFhyTGr 4KC7UXtt+XPDQHusE5JJXmUrqAkiSpTjghelEaoTMvkFprk5lgc+PY+dVl4271OltU 0kyY+X6KWUl9PTOcb+8XMLBSlbveJfMFlzJZkGV4G+psc1RPxOoJq2TIVoK/rkzDHg GVgXul98+yXn4EUZtmN0FhDQPW2JP7qg08PFsXJ9Odld72akvsjWQW4IH2S5yryckn mJaG/q7+7lIXISN+bigGlz6v8gP+fiJ5ZyyJ762CgZERnipv/AARB+4MYHKKkx/Ggw WZvduL/35S+Jg== Message-ID: <66d59de8-7fe8-4e8b-834c-9f0ed51ca5e0@kernel.org> Date: Fri, 10 Jul 2026 11:51:56 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: hamoa: Reserve low IOVA range for Iris From: Bryan O'Donoghue To: Vikash Garodia , Daniel J Blueman , Vikash Garodia Cc: Dikshita Agarwal , Abhinav Kumar , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260601041336.9497-1-daniel@quora.org> <20260601041336.9497-2-daniel@quora.org> Content-Language: en-US Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 09/06/2026 14:01, Bryan O'Donoghue wrote: > On 04/06/2026 07:38, Vikash Garodia wrote: >> >> >> On 6/2/2026 9:05 PM, Daniel J Blueman wrote: >>> On Tue, 2 Jun 2026 at 18:27, Bryan O'Donoghue wrote: >>>> >>>> On 01/06/2026 05:13, Daniel J Blueman wrote: >>>>> On X1-family hamoa platforms, Iris DMA below IOVA 0x25800000 (600MB) >>>>> triggers unhandled SMMU page faults >>>> >>>> How do we know that is a correct address - does it come from qcom >>>> documentation or trial and error ? >>> >>> @Vikash, beyond your comment I linked in the patch [1] kindly cite a >>> source for the different stream-ID <600MB behaviour, and share >>> specifics, eg if silicon, firmware, or driver and constraint, defect >>> or otherwise, so I can include a definitive description. >>> >>> Also good to know if my workaround is good for long-term, or on the >>> other hand handling streams <600MB is important/useful. >>> >> >> Thanks Daniel for raising this patch. Did you also try the memory fix i >> mentioned in the bug [1] discussion ? >> >> Coming to 600MB, this have been the VPU hardware restriction all the >> while since venus days, and since address could not go deeper all the >> way lower than 600MB, the issue never popped up earlier. >> >> Consider the memory layout split as below (Iris device range is capped >> to 0xe0000000) >> >> |-----600MB-----|-----(0xe0000000 - 600MB)-----|----IO reg--| >> >> 0-600MB range, VPU hardware would reserve this to generate different >> stream-IDs primarily for internal (non-pixel) buffers. >> >> 0-600 --> VPU would generate *secure* stream ID for non-pixel buffers >> 601 - 0xe0000000 --> VPU would generate non-secure stream ID for >> non-pixel buffers. >> >> When many concurrent sessions were tried, non-pixel buffers were mapped >> into 0-600MB range, and VPU generated secure ID for those. Since those >> were not associated with the iommus configured for iris node, it led to >> USF (un-identified stream fault) and device would crash. >> >> Keeping the region reserved, makes the non-pixel buffer always in the >> non secure range (601-..) and avoids the crash. >> >> Downside of this design - It would eventually reserve 0-600MB un-map >> 'able for all buffer types, like pixel as well which do not have any >> such restriction. >> >> Forward looking design - create devices dynamically and set reserve >> regions for those specific device using the api [1], instead of applying >> one reserve for all. >> >> [1] >> https://lore.kernel.org/all/20260119054936.3350128-1- >> busanna.reddy@oss.qualcomm.com/ > The problem here is in the reponse to the email you linked: > > https://lore.kernel.org/all/cfd23f75-8952-4463-abd5-815b995031b0@arm.com/ > > - Inheriting the parent's properties is wrong > - We should just have a bus > > But that leads us to churning DT and we'd have to figure out how/why to > do it purely for the purpose of differentiating SIDs within Iris. There > is no separate hardware - its one VPU which needs to figure out its IOVA > for different SIDs. > > Krzysztof would rightly say no - again - to putting collateral into DT > to differentiate pixel streams based on SID, because that's not a > hardware property. > > - You have pixel and non-pixel SIDs that have to hit Linux > - You have to keep non-pixel allocations >= 600 MB > - You can allow pixel < 600mb => >   Daniel's patch is too restrictive > > But what we can do is add information to the iris platform descriptors > to enumerate what are the valid IOVA ranges for pixel and non-pixel data > and then change the allocation code to operate from those platform-code > described IOVAs. > > No new iommu properties, not arguing about plonking SID/pixel-path data > into DT. > > Just teach the driver what the valid ranges are and allocate IOVAs based > on those ranges. > > I think Daniel's patch should be taken as it fixes a real bug for users > right now but, I equally think its a NAK for any new SoC. > > This IOVA allocation needs to be tackled correctly and IMO that needs to > be and should be done via platform descriptors for valid ranges of IOVA. > > No mad stuff about SIDs in DT, no lengthy arguments about adding strange > iommu properties. > > --- > bod Please pause merging this patch until this thread bottoms out https://lore.kernel.org/all/20260709-vpu_iommu_iova_handling-v1-7-72bb62cb2dfd@oss.qualcomm.com --- bod