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Wed, 21 Oct 2026 04:54:51 -0700 (PDT) Received: from [10.217.240.81] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1903d87ab1bsm6181635c88.21.2026.10.21.04.54.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 04:54:50 -0700 (PDT) Message-ID: <67404f33-9452-4a53-8ed6-8fee4eea2611@oss.qualcomm.com> Date: Wed, 21 Oct 2026 17:24:44 +0530 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets To: Krzysztof Kozlowski Cc: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Borislav Petkov , Tony Luck , Conor Dooley , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org References: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com> <20261014-master-v1-2-aba3cfcfbac9@oss.qualcomm.com> <20261017-spiffy-shapeless-caiman-d658a6@quoll> Content-Language: en-US From: Faiyaz Mohammed In-Reply-To: <20261017-spiffy-shapeless-caiman-d658a6@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: -7fGIaM5RLQy-HvVyX7_GsoJ0DCfvt_G X-Proofpoint-GUID: -7fGIaM5RLQy-HvVyX7_GsoJ0DCfvt_G X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfX8wuNVWMNEviu FKHaOGwEvetA2zNeRFeck0EvDFbNd4KSjFmJ3kA9W7QeeNxlrfmzWiYieR9+4RpnBxmOao/iRCp WXzv+OuvDuCEyMkIjL9e9LrVl181cpo= X-Authority-Analysis: v=2.4 cv=R7aWitRX c=1 sm=1 tr=0 ts=6ad8a80c cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=VlAtpL-8CsKfw-zIKP4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfX/VtAgs05GrVo EjJaU5BwiJlB3xYJuujECwhb/aQbAlTDKSKyEYSIUugz0jRdJ/Ul5tbjYI0xNCyuTEUjl/mwg/R 7HJsTiivLnLHtrYSE5IskzZQ+Jf3akIywyyqDLsP8djqauQ5vl1f5J6NYto1sATx0m1HiIJUWmy eDbp8Fv2TaF6kRiuxBwIEepW8E8vXMFks9qsxEezLofhTxRIkkGx9aXWKiwubKyKtnZ5z1l3hSP TLy/KsMXMhWHdXaFII0Mog3jI6fS6ZpE262CTr9Fp9WCPPwcNP4jCbtoRNrCv4wPEY+EkvYU2Cy tobxJZv+/lhkwG11i2NU2kbt8wlJw+BYgxhriFg4n4L6vCGif3j/2R+AqPwdvgKpVnmgOr77MTF KypBJMsh1t2ST+WVSvxSsvB9jPCW9Cp1e2yF9nkIFxviJdnkdamOAT3rw4cC5cCwz6xzzdhT7f/ U5hvK2ZIEx10ESjpdCQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_03,2026-10-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210047 On 17-10-2026 22:04, Krzysztof Kozlowski wrote: > On Wed, Oct 14, 2026 at 09:26:17PM +0530, Faiyaz Mohammed wrote: >> Add LCP/SRP ECC register offsets to struct llcc_edac_reg_offset and >> create llcc_lcp_srp_edac_reg_offset for QCM2390, leaving the shared >> llcc_v2_1_edac_reg_offset table unchanged. Switch shikra_cfg to the >> new table so other platforms with the same block can reuse it. >> >> Add lcp_irq to struct llcc_drv_data and retrieve the optional second >> interrupt in qcom_llcc_probe(), propagating non-absence errors so the >> driver defers correctly. >> >> Signed-off-by: Faiyaz Mohammed >> --- >> drivers/soc/qcom/llcc-qcom.c | 45 ++++++++++++++++++++++++++++++++++++-- >> include/linux/soc/qcom/llcc-qcom.h | 13 +++++++++++ >> 2 files changed, 56 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c >> index d7a42a8040a1..39e0da14b36d 100644 >> --- a/drivers/soc/qcom/llcc-qcom.c >> +++ b/drivers/soc/qcom/llcc-qcom.c >> @@ -4509,6 +4509,41 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { >> .drp_ecc_db_err_syn0 = 0x52120, >> }; >> >> +static const struct llcc_edac_reg_offset llcc_lcp_srp_edac_reg_offset = { >> + .trp_ecc_error_status0 = 0x20344, >> + .trp_ecc_error_status1 = 0x20348, >> + .trp_ecc_sb_err_syn0 = 0x2034c, >> + .trp_ecc_db_err_syn0 = 0x20370, >> + .trp_ecc_error_cntr_clear = 0x20440, >> + .trp_interrupt_0_status = 0x20480, >> + .trp_interrupt_0_clear = 0x20484, >> + .trp_interrupt_0_enable = 0x20488, >> + >> + /* LLCC Common registers */ >> + .cmn_status0 = 0x3400c, >> + .cmn_interrupt_0_enable = 0x3401c, >> + .cmn_interrupt_1_enable = 0x3402c, >> + .cmn_interrupt_2_enable = 0x3403c, >> + >> + /* LLCC DRP registers */ >> + .drp_ecc_error_cfg = 0x50000, >> + .drp_ecc_error_cntr_clear = 0x50004, >> + .drp_interrupt_status = 0x50020, >> + .drp_interrupt_clear = 0x50028, >> + .drp_interrupt_enable = 0x5002c, >> + .drp_ecc_error_status0 = 0x520f4, >> + .drp_ecc_error_status1 = 0x520f8, >> + .drp_ecc_sb_err_syn0 = 0x520fc, >> + .drp_ecc_db_err_syn0 = 0x52120, >> + >> + /* LCP/SRP DDR DRAM ECC registers */ >> + .lcp_srp_ecc_error_cntr_clear = 0x59004, >> + .lcp_srp_ecc_error_status1 = 0x59010, >> + .lcp_srp_interrupt_status = 0x59070, >> + .lcp_srp_interrupt_clear = 0x59074, >> + .lcp_srp_interrupt_enable = 0x59078, >> +}; >> + >> static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = { >> .trp_ecc_error_status0 = 0x47448, >> .trp_ecc_error_status1 = 0x47450, >> @@ -4767,7 +4802,7 @@ static const struct qcom_llcc_config shikra_cfg[] = { >> .sct_data = shikra_data, >> .size = ARRAY_SIZE(shikra_data), >> .reg_offset = llcc_v2_1_reg_offset, >> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, >> + .edac_reg_offset = &llcc_lcp_srp_edac_reg_offset, >> .irq_configured = true, >> }, >> }; >> @@ -5798,7 +5833,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) >> if (drv_data->ecc_irq < 0 && drv_data->ecc_irq != -ENXIO) >> return dev_err_probe(&pdev->dev, drv_data->ecc_irq, >> "failed to get IRQ resource\n"); >> - >> + if (cfg->edac_reg_offset && cfg->edac_reg_offset->lcp_srp_interrupt_enable) { >> + drv_data->lcp_irq = platform_get_irq_optional(pdev, 1); > > Why do you exactly require interrupt-names? > Good question. The driver was using platform_get_irq_optional(pdev, 1) by index, which made interrupt-names a documentation-only annotation with no driver enforcement — not a good reason to require it. Switched lcp_irq retrieval to platform_get_irq_byname_optional(pdev, "lcp"). Platforms without interrupt-names naturally return -ENODATA, which the driver treats as absent — no explicit register-offset guard needed. The ecc_irq stays index-based (platform_get_irq_optional(pdev, 0)) for backward compatibility with all legacy platforms that have no interrupt-names property. Will repost as v2. > Best regards, > Krzysztof Thanks & regards, Mohammed Faiyaz