Re: Re: [PATCH v9 2/2] PCI: eic7700: Add Eswin PCIe host controller driver

[zhangsenchuan <zhangsenchuan@eswincomputing.com>]

+cc Sumit

> On Tue, Jan 06, 2026 at 08:43:11PM +0800, zhangsenchuan wrote:
> > > Subject: Re: [PATCH v9 2/2] PCI: eic7700: Add Eswin PCIe host controller driver
> > > 
> > > [+cc Niklas, list vs array of ports]
> > > 
> > > On Mon, Dec 29, 2025 at 07:32:07PM +0800, zhangsenchuan@eswincomputing.com wrote:
> > > > From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
> > > > 
> > > > Add driver for the Eswin EIC7700 PCIe host controller, which is based on
> > > > the DesignWare PCIe core, IP revision 5.96a. The PCIe Gen.3 controller
> > > > supports a data rate of 8 GT/s and 4 channels, support INTx and MSI
> > > > interrupts.
> > > 
> > > > +static int eic7700_pcie_parse_port(struct eic7700_pcie *pcie,
> > > > +				   struct device_node *node)
> > > > +{
> > > > +	struct device *dev = pcie->pci.dev;
> > > > +	struct eic7700_pcie_port *port;
> > > > +
> > > > +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > > > +	if (!port)
> > > > +		return -ENOMEM;
> > > > +
> > > > +	port->perst = of_reset_control_get_exclusive(node, "perst");
> > > > +	if (IS_ERR(port->perst)) {
> > > > +		dev_err(dev, "Failed to get PERST# reset\n");
> > > > +		return PTR_ERR(port->perst);
> > > > +	}
> > > > +
> > > > +	/*
> > > > +	 * TODO: Since the Root Port node is separated out by pcie devicetree,
> > > > +	 * the DWC core initialization code can't parse the num-lanes attribute
> > > > +	 * in the Root Port. Before entering the DWC core initialization code,
> > > > +	 * the platform driver code parses the Root Port node. The EIC7700 only
> > > > +	 * supports one Root Port node, and the num-lanes attribute is suitable
> > > > +	 * for the case of one Root Port.
> > > > +	 */
> > > > +	if (!of_property_read_u32(node, "num-lanes", &port->num_lanes))
> > > > +		pcie->pci.num_lanes = port->num_lanes;
> > > > +
> > > > +	INIT_LIST_HEAD(&port->list);
> > > > +	list_add_tail(&port->list, &pcie->ports);
> > > 
> > > Niklas raised an interesting question about whether a list or an array
> > > is the best data structure for the set of Root Ports:
> > > 
> > >   https://lore.kernel.org/r/aVvkmkd5mWPmxeiS@ryzen
> > > 
> > > Might have to iterate over the child nodes twice (once to count, again
> > > for eic7700_pcie_parse_port()), but otherwise the array is probably
> > > simpler code.
> > 
> > After reading patch's comments, lists and arrays seem to be good choices,
> > I don't have any particularly good ideas for the time being. Anyway, this
> > is a very good patch that supports multiple Root Ports resolutions.
> > 
> 
> I still prefer using lists for the reasons mentioned in that thread.

Lists and arrays do not have too obvious disadvantages. For me, i prefer
to use list. We can use the standard kernel linked list API, which has a 
rich set of helper functions. It is developer-friendly and does not require 
familiarity with other API.

In addition, I saw that the device nodes "amd,versal2-mdb-host.yaml" and 
"sophgo,sg2044-pcie.yaml" have nodes that are not Port. Will this affect 
the node traversal?

Kind regards,
Senchuan

> 
> > > 
> > > > +	return 0;
> > > > +}