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Mon, 09 Dec 2024 07:56:22 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B97uL0V012615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 07:56:21 GMT Received: from [10.64.68.72] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 8 Dec 2024 23:56:15 -0800 Message-ID: <677251eb-d3c3-48e1-ba79-fb8ec1e29c6f@quicinc.com> Date: Mon, 9 Dec 2024 15:56:13 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: qcs615: add UFS node To: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio CC: Vinod Koul , Kishon Vijay Abraham I , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross , , , , , , , , , References: <20241122064428.278752-1-quic_liuxin@quicinc.com> <20241122064428.278752-3-quic_liuxin@quicinc.com> From: Xin Liu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fhcH6imOFbF_y0RnyThXz3P6qCy6QLoS X-Proofpoint-GUID: fhcH6imOFbF_y0RnyThXz3P6qCy6QLoS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090060 在 2024/12/6 5:21, Konrad Dybcio 写道: > On 22.11.2024 7:44 AM, Xin Liu wrote: >> From: Sayali Lokhande >> >> Add the UFS Host Controller node and its PHY for QCS615 SoC. >> >> Signed-off-by: Sayali Lokhande >> Co-developed-by: Xin Liu >> Signed-off-by: Xin Liu >> --- > > [...] > >> + >> + operating-points-v2 = <&ufs_opp_table>; >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > > QCOM_ICC_TAG_ACTIVE_ONLY for the cpu path I need to ask you for advice. I have reviewed the ufs_mem_hc of many devices and found that all of them use QCOM_ICC_TAG_ALWAYS for their interconnects cpu path. Why do I need to use QCOM_ICC_TAG_ACTIVE_ONLY here? > >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; > > this contradicts the levels in the OPP table: The required-opps here corresponds to opp-200000000 in the opp_table below. Similarly, I referred to sm8550.dtsi, whose required-opps also corresponds to the opp table. > >> + >> + iommus = <&apps_smmu 0x300 0x0>; >> + dma-coherent; >> + >> + lanes-per-direction = <1>; >> + >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + >> + #reset-cells = <1>; >> + >> + status = "disabled"; >> + >> + ufs_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-50000000 { >> + opp-hz = /bits/ 64 <50000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <37500000>, >> + /bits/ 64 <75000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + > > Konrad