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Thu, 14 Aug 2025 01:37:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C8.mail.protection.outlook.com (10.167.240.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9031.11 via Frontend Transport; Thu, 14 Aug 2025 01:37:39 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 566E740A5A30; Thu, 14 Aug 2025 09:37:38 +0800 (CST) Message-ID: <67928928-6e75-4683-9445-0c25a9d606b4@cixtech.com> Date: Thu, 14 Aug 2025 09:37:38 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 00/13] Enhance the PCIe controller driver for next generation controllers To: Krzysztof Kozlowski , bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2025 01:37:39.0960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63e9ebef-d79d-4ac4-5a0f-08dddad3278d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB6663 On 2025/8/14 03:14, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On 13/08/2025 06:23, hans.zhang@cixtech.com wrote: >> From: Hans Zhang >> >> --- >> Dear Maintainers, >> >> This series is Cadence's HPA PCIe IP and the Root Port driver of our >> CIX sky1. Please help review. Thank you very much. >> --- >> >> Enhances the exiting Cadence PCIe controller drivers to support >> HPA (High Performance Architecture) Cadence PCIe controllers. >> >> The patch set enhances the Cadence PCIe driver for HPA support. >> The header files are separated out for legacy and high performance >> register maps, register address and bit definitions. The driver >> read register and write register functions for HPA take the >> updated offset stored from the platform driver to access the registers. >> As part of refactoring of the code, few new files are added to the >> driver by splitting the existing files. >> This helps SoC vendor who change the address map within PCIe controller >> in their designs. Setting the menuconfig appropriately will allow >> selection between RP and/or EP PCIe controller support. The support >> will include Legacy and HPA for the selected configuration. >> >> The TI SoC continues to be supported with the changes incorporated. >> >> The changes address the review comments in the previous patches where >> the need to move away from "ops" pointers used in current implementation >> and separate out the Legacy and HPA driver implementation was stressed. >> >> The scripts/checkpatch.pl has been run on the patches with and without >> --strict. With the --strict option, 4 checks are generated on 2 patch, >> which can be ignored. There are no code fixes required for these checks. >> All other checks generated by ./scripts/checkpatch.pl --strict can be >> ignored. >> >> --- >> Changes for v7 >> - Rebase to v6.17-rc1. >> - Fixed the error issue of cix,sky1-pcie-host.yaml make dt_binding_check. >> - CIX SKY1 Root Port driver compilation error issue: Add header >> file, Kconfig select PCI_ECAM. >> > > Where are lore links to all previous versions? Dear Krzysztof, I will add it in all future versions. V6: https://patchwork.kernel.org/project/linux-pci/cover/20250808072929.4090694-1-hans.zhang@cixtech.com/ V5: https://patchwork.kernel.org/project/linux-pci/cover/20250630041601.399921-1-hans.zhang@cixtech.com/ V4: https://patchwork.kernel.org/project/linux-pci/cover/20250424010445.2260090-1-hans.zhang@cixtech.com/ V3: https://patchwork.kernel.org/project/linux-pci/patch/20250411103656.2740517-1-hans.zhang@cixtech.com/ Best regards, Hans