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From: Christian Marangi <ansuelsmth@gmail.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>, Lee Jones <lee@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Vladimir Oltean <olteanv@gmail.com>,
	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	upstream@airoha.com
Subject: Re: [net-next PATCH v12 07/13] net: mdio: regmap: add support for multiple valid addr
Date: Fri, 14 Mar 2025 22:19:29 +0100	[thread overview]
Message-ID: <67d49d64.050a0220.35694d.b7ab@mx.google.com> (raw)
In-Reply-To: <Z9SZRDykbTwvGW6S@shell.armlinux.org.uk>

On Fri, Mar 14, 2025 at 09:01:56PM +0000, Russell King (Oracle) wrote:
> On Fri, Mar 14, 2025 at 08:41:33PM +0100, Andrew Lunn wrote:
> > On Sun, Mar 09, 2025 at 06:45:43PM +0100, Christian Marangi wrote:
> > > On Sun, Mar 09, 2025 at 05:36:49PM +0000, Russell King (Oracle) wrote:
> > > > On Sun, Mar 09, 2025 at 06:26:52PM +0100, Christian Marangi wrote:
> > > > > +/* If a non empty valid_addr_mask is passed, PHY address and
> > > > > + * read/write register are encoded in the regmap register
> > > > > + * by placing the register in the first 16 bits and the PHY address
> > > > > + * right after.
> > > > > + */
> > > > > +#define MDIO_REGMAP_PHY_ADDR		GENMASK(20, 16)
> > > > > +#define MDIO_REGMAP_PHY_REG		GENMASK(15, 0)
> > > > 
> > > > Clause 45 PHYs have 5 bits of PHY address, then 5 bits of mmd address,
> > > > and then 16 bits of register address - significant in that order. Can
> > > > we adjust the mask for the PHY address later to add the MMD between
> > > > the PHY address and register number?
> > > >
> > > 
> > > Honestly to future proof this, I think a good idea might be to add
> > > helper to encode these info and use Clause 45 format even for C22.
> > > Maybe we can use an extra bit to signal if the format is C22 or C45.
> > > 
> > > BIT(26) 0: C22 1:C45
> > > GENMASK(25, 21) PHY ADDR
> > > GENMASK(20, 16) MMD ADDR
> > > GENMASK(15, 0) REG
> > 
> > If you look back at older kernels, there was some helpers to do
> > something like this, but the C22/C45 was in bit 31. When i cleaned up
> > MDIO drivers to have separate C22 and C45 read/write functions, they
> > become redundant and they were removed. You might want to bring them
> > back again.
> 
> I'd prefer we didn't bring that abomination back. The detail about how
> things are stored in regmap should be internal within regmap, and I
> think it would be better to have an API presented that takes sensible
> parameters, rather than something that's been encoded.
>

Well problem is that regmap_write and regmap_read will take max 2 value
at the very end (reg and value) so it's really a matter of making the
encoding part internal but encoding it can't be skipped.

You are suggesting to introduce additional API like

mdio_regmap_write(regmap, phy, addr, val);
mdio_mmd_regmap_write(regmap, phy, mmd, addr, val);

And the encoding is done internally?

My concern is the decoding part from the .write/read_bits regmap OPs.
I guess for that also some helper should be exposed (to keep the
decoding/encoding internal to the driver and not expose the
_abomination_)

What do you think?

-- 
	Ansuel

  reply	other threads:[~2025-03-14 21:19 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-09 17:26 [net-next PATCH v12 00/13] net: dsa: Add Airoha AN8855 support Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 01/13] dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 02/13] dt-bindings: net: Document support for Airoha AN8855 Switch Virtual MDIO Christian Marangi
2025-03-20 17:31   ` Simon Horman
2025-03-09 17:26 ` [net-next PATCH v12 03/13] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
2025-03-11 19:20   ` Rob Herring
2025-03-20 17:32   ` Simon Horman
2025-03-09 17:26 ` [net-next PATCH v12 04/13] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
2025-03-11 19:25   ` Rob Herring
2025-03-09 17:26 ` [net-next PATCH v12 05/13] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
2025-03-09 18:50   ` Rob Herring (Arm)
2025-03-09 19:26   ` kernel test robot
2025-03-09 17:26 ` [net-next PATCH v12 06/13] net: mdio: regmap: prepare support for multiple valid addr Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 07/13] net: mdio: regmap: add " Christian Marangi
2025-03-09 17:36   ` Russell King (Oracle)
2025-03-09 17:45     ` Christian Marangi
2025-03-14 19:41       ` Andrew Lunn
2025-03-14 21:01         ` Russell King (Oracle)
2025-03-14 21:19           ` Christian Marangi [this message]
2025-03-14 22:25             ` Russell King (Oracle)
2025-03-09 17:26 ` [net-next PATCH v12 08/13] net: mdio: regmap: add OF support Christian Marangi
2025-03-09 17:37   ` Russell King (Oracle)
2025-03-09 17:48     ` Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 09/13] mfd: an8855: Add support for Airoha AN8855 Switch MFD Christian Marangi
2025-03-14 11:35   ` Lee Jones
2025-03-14 19:34     ` Andrew Lunn
2025-03-15 10:52     ` Christian Marangi
2025-03-14 19:16   ` Andrew Lunn
2025-03-09 17:26 ` [net-next PATCH v12 10/13] net: mdio: Add Airoha AN8855 Switch MDIO Passtrough Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 11/13] nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE Christian Marangi
2025-03-09 17:26 ` [net-next PATCH v12 12/13] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
2025-03-09 17:57   ` Russell King (Oracle)
2025-03-10 10:57     ` Christian Marangi
2025-03-10 11:05       ` Russell King (Oracle)
2025-03-09 17:26 ` [net-next PATCH v12 13/13] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi

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