[PATCH V3 0/4] Add UFS support for x1e80100 SoC

[PATCH V3 0/4] Add UFS support for x1e80100 SoC

[Pradeep P V K]

Add UFSPHY, UFSHC compatible binding names and UFS devicetree
enablement changes for Qualcomm x1e80100 SoC.

Changes in V3:
- Update all dt-bindings commit messages with concise and informative
  statements [Krzysztof]
- keep the QMP UFS PHY order by last compatible in numerical ascending
  order [Krzysztof]
- Remove qcom,x1e80100-ufshc from select: enum: list of
  qcom,sc7180-ufshc.yaml file [Krzysztof]
- Update subject prefix for all dt-bindings [Krzysztof]
- Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
- Add RB-by for board dts [Konrad]
- Link to V2:
  https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com

---
Pradeep P V K (4):
  dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
    compatible
  dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
  arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
  arm64: dts: qcom: hamoa-iot-evk: Enable UFS

 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   4 +
 .../bindings/ufs/qcom,sc7180-ufshc.yaml       |  37 +++---
 arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts    |  18 +++
 arch/arm64/boot/dts/qcom/hamoa.dtsi           | 123 +++++++++++++++++-
 4 files changed, 164 insertions(+), 18 deletions(-)

-- 
2.34.1

[PATCH V3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible

[Pradeep P V K]

Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a
fallback since x1e80100 is fully compatible with it.

Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index fba7b2549dde..166e3787db58 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -20,6 +20,10 @@ properties:
           - enum:
               - qcom,qcs615-qmp-ufs-phy
           - const: qcom,sm6115-qmp-ufs-phy
+      - items:
+          - enum:
+              - qcom,x1e80100-qmp-ufs-phy
+          - const: qcom,sm8550-qmp-ufs-phy
       - items:
           - enum:
               - qcom,qcs8300-qmp-ufs-phy
-- 
2.34.1

[PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100

[Pradeep P V K]

Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
SM8550 as a fallback since x1e80100 is fully compatible with it.

Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
 .../bindings/ufs/qcom,sc7180-ufshc.yaml       | 37 +++++++++++--------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
index d94ef4e6b85a..c1085d178421 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -31,21 +31,28 @@ select:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - qcom,msm8998-ufshc
-          - qcom,qcs8300-ufshc
-          - qcom,sa8775p-ufshc
-          - qcom,sc7180-ufshc
-          - qcom,sc7280-ufshc
-          - qcom,sc8180x-ufshc
-          - qcom,sc8280xp-ufshc
-          - qcom,sm8250-ufshc
-          - qcom,sm8350-ufshc
-          - qcom,sm8450-ufshc
-          - qcom,sm8550-ufshc
-      - const: qcom,ufshc
-      - const: jedec,ufs-2.0
+    oneOf:
+      - items:
+          - enum:
+              - qcom,x1e80100-ufshc
+          - const: qcom,sm8550-ufshc
+          - const: qcom,ufshc
+          - const: jedec,ufs-2.0
+      - items:
+          - enum:
+              - qcom,msm8998-ufshc
+              - qcom,qcs8300-ufshc
+              - qcom,sa8775p-ufshc
+              - qcom,sc7180-ufshc
+              - qcom,sc7280-ufshc
+              - qcom,sc8180x-ufshc
+              - qcom,sc8280xp-ufshc
+              - qcom,sm8250-ufshc
+              - qcom,sm8350-ufshc
+              - qcom,sm8450-ufshc
+              - qcom,sm8550-ufshc
+          - const: qcom,ufshc
+          - const: jedec,ufs-2.0
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Pradeep P V K]

Add UFS host controller and PHY nodes for x1e80100 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
 1 file changed, 120 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index f7d71793bc77..33899fa06aa4 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <0>,
 				 <0>,
-				 <0>,
-				 <0>,
-				 <0>;
+				 <&ufs_mem_phy 0>,
+				 <&ufs_mem_phy 1>,
+				 <&ufs_mem_phy 2>;
 
 			power-domains = <&rpmhpd RPMHPD_CX>;
 			#clock-cells = <1>;
@@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
 			status = "disabled";
 		};
 
+		ufs_mem_phy: phy@1d80000 {
+			compatible = "qcom,x1e80100-qmp-ufs-phy",
+				     "qcom,sm8550-qmp-ufs-phy";
+			reg = <0x0 0x01d80000 0x0 0x2000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
+
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,x1e80100-ufshc",
+				     "qcom,sm8550-ufshc",
+				     "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>;
+
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmhcc RPMH_LN_BB_CLK3>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "rx_lane1_sync_clk";
+
+			operating-points-v2 = <&ufs_opp_table>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			iommus = <&apps_smmu 0x1a0 0>;
+			dma-coherent;
+
+			lanes-per-direction = <2>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			#reset-cells = <1>;
+
+			status = "disabled";
+
+			ufs_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-75000000 {
+					opp-hz = /bits/ 64 <75000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <75000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-150000000 {
+					opp-hz = /bits/ 64 <150000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <150000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-300000000 {
+					opp-hz = /bits/ 64 <300000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <300000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
 		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x0 0x01dc4000 0x0 0x28000>;
-- 
2.34.1

[PATCH V3 4/4] arm64: dts: qcom: hamoa-iot-evk: Enable UFS

[Pradeep P V K]

Enable UFS for HAMOA-IOT-EVK board.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
index 88e3e7bed998..23cd913b05f5 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
+++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
@@ -1253,6 +1253,24 @@ &uart21 {
 	status = "okay";
 };
 
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>;
+
+	vcc-supply = <&vreg_l17b_2p5>;
+	vcc-max-microamp = <1300000>;
+	vccq-supply = <&vreg_l2i_1p2>;
+	vccq-max-microamp = <1200000>;
+
+	status = "okay";
+};
+
 &usb_1_ss0_dwc3_hs {
 	remote-endpoint = <&pmic_glink_ss0_hs_in>;
 };
-- 
2.34.1

Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC

[Dmitry Baryshkov]

On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
> enablement changes for Qualcomm x1e80100 SoC.
> 
> Changes in V3:
> - Update all dt-bindings commit messages with concise and informative
>   statements [Krzysztof]
> - keep the QMP UFS PHY order by last compatible in numerical ascending
>   order [Krzysztof]
> - Remove qcom,x1e80100-ufshc from select: enum: list of
>   qcom,sc7180-ufshc.yaml file [Krzysztof]
> - Update subject prefix for all dt-bindings [Krzysztof]
> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
> - Add RB-by for board dts [Konrad]
> - Link to V2:
>   https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com

Where did the previous changelog go?

> 
> ---
> Pradeep P V K (4):
>   dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
>     compatible
>   dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
>   arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
>   arm64: dts: qcom: hamoa-iot-evk: Enable UFS
> 
>  .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   4 +
>  .../bindings/ufs/qcom,sc7180-ufshc.yaml       |  37 +++---
>  arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts    |  18 +++
>  arch/arm64/boot/dts/qcom/hamoa.dtsi           | 123 +++++++++++++++++-
>  4 files changed, 164 insertions(+), 18 deletions(-)
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH V3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible

[Krzysztof Kozlowski]

On Mon, Jan 05, 2026 at 08:16:40PM +0530, Pradeep P V K wrote:
> Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a
> fallback since x1e80100 is fully compatible with it.
> 
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml    | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100

[Krzysztof Kozlowski]

On Mon, Jan 05, 2026 at 08:16:41PM +0530, Pradeep P V K wrote:
> Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
> SM8550 as a fallback since x1e80100 is fully compatible with it.
> 
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
>  .../bindings/ufs/qcom,sc7180-ufshc.yaml       | 37 +++++++++++--------
>  1 file changed, 22 insertions(+), 15 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100

[Manivannan Sadhasivam]

On Mon, Jan 05, 2026 at 08:16:41PM +0530, Pradeep P V K wrote:
> Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
> SM8550 as a fallback since x1e80100 is fully compatible with it.
> 
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> ---
>  .../bindings/ufs/qcom,sc7180-ufshc.yaml       | 37 +++++++++++--------
>  1 file changed, 22 insertions(+), 15 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> index d94ef4e6b85a..c1085d178421 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> @@ -31,21 +31,28 @@ select:
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - qcom,msm8998-ufshc
> -          - qcom,qcs8300-ufshc
> -          - qcom,sa8775p-ufshc
> -          - qcom,sc7180-ufshc
> -          - qcom,sc7280-ufshc
> -          - qcom,sc8180x-ufshc
> -          - qcom,sc8280xp-ufshc
> -          - qcom,sm8250-ufshc
> -          - qcom,sm8350-ufshc
> -          - qcom,sm8450-ufshc
> -          - qcom,sm8550-ufshc
> -      - const: qcom,ufshc
> -      - const: jedec,ufs-2.0
> +    oneOf:
> +      - items:
> +          - enum:
> +              - qcom,x1e80100-ufshc
> +          - const: qcom,sm8550-ufshc
> +          - const: qcom,ufshc
> +          - const: jedec,ufs-2.0
> +      - items:
> +          - enum:
> +              - qcom,msm8998-ufshc
> +              - qcom,qcs8300-ufshc
> +              - qcom,sa8775p-ufshc
> +              - qcom,sc7180-ufshc
> +              - qcom,sc7280-ufshc
> +              - qcom,sc8180x-ufshc
> +              - qcom,sc8280xp-ufshc
> +              - qcom,sm8250-ufshc
> +              - qcom,sm8350-ufshc
> +              - qcom,sm8450-ufshc
> +              - qcom,sm8550-ufshc
> +          - const: qcom,ufshc
> +          - const: jedec,ufs-2.0
>  
>    reg:
>      maxItems: 1
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Manivannan Sadhasivam]

On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
> Add UFS host controller and PHY nodes for x1e80100 SoC.
> 

Minor nits below. With those fixed,

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
>  1 file changed, 120 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index f7d71793bc77..33899fa06aa4 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
>  				 <0>,
>  				 <0>,
>  				 <0>,
> -				 <0>,
> -				 <0>,
> -				 <0>;
> +				 <&ufs_mem_phy 0>,
> +				 <&ufs_mem_phy 1>,
> +				 <&ufs_mem_phy 2>;
>  
>  			power-domains = <&rpmhpd RPMHPD_CX>;
>  			#clock-cells = <1>;
> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
>  			status = "disabled";
>  		};
>  
> +		ufs_mem_phy: phy@1d80000 {
> +			compatible = "qcom,x1e80100-qmp-ufs-phy",
> +				     "qcom,sm8550-qmp-ufs-phy";
> +			reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> +
> +			clock-names = "ref",
> +				      "ref_aux",
> +				      "qref";
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +
> +			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> +
> +			#clock-cells = <1>;
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +		};
> +
> +		ufs_mem_hc: ufs@1d84000 {

ufshc@

> +			compatible = "qcom,x1e80100-ufshc",
> +				     "qcom,sm8550-ufshc",
> +				     "qcom,ufshc",
> +				     "jedec,ufs-2.0";

Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
driver.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Pradeep Pragallapati]

On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
> On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
>> Add UFS host controller and PHY nodes for x1e80100 SoC.
>>
> 
> Minor nits below. With those fixed,
> 
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> 
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
>>   1 file changed, 120 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> index f7d71793bc77..33899fa06aa4 100644
>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
>>   				 <0>,
>>   				 <0>,
>>   				 <0>,
>> -				 <0>,
>> -				 <0>,
>> -				 <0>;
>> +				 <&ufs_mem_phy 0>,
>> +				 <&ufs_mem_phy 1>,
>> +				 <&ufs_mem_phy 2>;
>>   
>>   			power-domains = <&rpmhpd RPMHPD_CX>;
>>   			#clock-cells = <1>;
>> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
>>   			status = "disabled";
>>   		};
>>   
>> +		ufs_mem_phy: phy@1d80000 {
>> +			compatible = "qcom,x1e80100-qmp-ufs-phy",
>> +				     "qcom,sm8550-qmp-ufs-phy";
>> +			reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>> +
>> +			clock-names = "ref",
>> +				      "ref_aux",
>> +				      "qref";
>> +			resets = <&ufs_mem_hc 0>;
>> +			reset-names = "ufsphy";
>> +
>> +			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
>> +
>> +			#clock-cells = <1>;
>> +			#phy-cells = <0>;
>> +
>> +			status = "disabled";
>> +		};
>> +
>> +		ufs_mem_hc: ufs@1d84000 {
> 
> ufshc@
ok, i will update in the next patchset.
> 
>> +			compatible = "qcom,x1e80100-ufshc",
>> +				     "qcom,sm8550-ufshc",
>> +				     "qcom,ufshc",
>> +				     "jedec,ufs-2.0";
> 
> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
> driver.
"jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead 
to dtbs_check failures. is it ok, if i continue with it ?
> 
> - Mani
> 

Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC

[Pradeep Pragallapati]

On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
>> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
>> enablement changes for Qualcomm x1e80100 SoC.
>>
>> Changes in V3:
>> - Update all dt-bindings commit messages with concise and informative
>>    statements [Krzysztof]
>> - keep the QMP UFS PHY order by last compatible in numerical ascending
>>    order [Krzysztof]
>> - Remove qcom,x1e80100-ufshc from select: enum: list of
>>    qcom,sc7180-ufshc.yaml file [Krzysztof]
>> - Update subject prefix for all dt-bindings [Krzysztof]
>> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
>> - Add RB-by for board dts [Konrad]
>> - Link to V2:
>>    https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
> 
> Where did the previous changelog go?
i missed to amend, i will update all changelog in my next patchset.
> 
>>
>> ---
>> Pradeep P V K (4):
>>    dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
>>      compatible
>>    dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
>>    arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
>>    arm64: dts: qcom: hamoa-iot-evk: Enable UFS
>>
>>   .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   4 +
>>   .../bindings/ufs/qcom,sc7180-ufshc.yaml       |  37 +++---
>>   arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts    |  18 +++
>>   arch/arm64/boot/dts/qcom/hamoa.dtsi           | 123 +++++++++++++++++-
>>   4 files changed, 164 insertions(+), 18 deletions(-)
>>
>> -- 
>> 2.34.1
>>
> 

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Krzysztof Kozlowski]

On 06/01/2026 14:00, Pradeep Pragallapati wrote:
>>
>>> +			compatible = "qcom,x1e80100-ufshc",
>>> +				     "qcom,sm8550-ufshc",
>>> +				     "qcom,ufshc",
>>> +				     "jedec,ufs-2.0";
>>
>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>> driver.
> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead 
> to dtbs_check failures. is it ok, if i continue with it ?

No, it is not ok. You cannot have errors/warnings and I think it is
obvious that you need to fix everything, not only DTS.

Best regards,
Krzysztof

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Pradeep Pragallapati]

On 1/6/2026 7:10 PM, Krzysztof Kozlowski wrote:
> On 06/01/2026 14:00, Pradeep Pragallapati wrote:
>>>
>>>> +			compatible = "qcom,x1e80100-ufshc",
>>>> +				     "qcom,sm8550-ufshc",
>>>> +				     "qcom,ufshc",
>>>> +				     "jedec,ufs-2.0";
>>>
>>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>>> driver.
>> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead
>> to dtbs_check failures. is it ok, if i continue with it ?
> 
> No, it is not ok. You cannot have errors/warnings and I think it is
> obvious that you need to fix everything, not only DTS.
sure, i will update in my next patchset.
> 
> Best regards,
> Krzysztof

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Manivannan Sadhasivam]

On Tue, Jan 06, 2026 at 06:30:05PM +0530, Pradeep Pragallapati wrote:
> 
> 
> On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
> > On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
> > > Add UFS host controller and PHY nodes for x1e80100 SoC.
> > > 
> > 
> > Minor nits below. With those fixed,
> > 
> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > 
> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > > Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > > Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > > Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> > > ---
> > >   arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
> > >   1 file changed, 120 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > index f7d71793bc77..33899fa06aa4 100644
> > > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > > @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
> > >   				 <0>,
> > >   				 <0>,
> > >   				 <0>,
> > > -				 <0>,
> > > -				 <0>,
> > > -				 <0>;
> > > +				 <&ufs_mem_phy 0>,
> > > +				 <&ufs_mem_phy 1>,
> > > +				 <&ufs_mem_phy 2>;
> > >   			power-domains = <&rpmhpd RPMHPD_CX>;
> > >   			#clock-cells = <1>;
> > > @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
> > >   			status = "disabled";
> > >   		};
> > > +		ufs_mem_phy: phy@1d80000 {
> > > +			compatible = "qcom,x1e80100-qmp-ufs-phy",
> > > +				     "qcom,sm8550-qmp-ufs-phy";
> > > +			reg = <0x0 0x01d80000 0x0 0x2000>;
> > > +
> > > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > > +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
> > > +
> > > +			clock-names = "ref",
> > > +				      "ref_aux",
> > > +				      "qref";
> > > +			resets = <&ufs_mem_hc 0>;
> > > +			reset-names = "ufsphy";
> > > +
> > > +			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> > > +
> > > +			#clock-cells = <1>;
> > > +			#phy-cells = <0>;
> > > +
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		ufs_mem_hc: ufs@1d84000 {
> > 
> > ufshc@
> ok, i will update in the next patchset.
> > 
> > > +			compatible = "qcom,x1e80100-ufshc",
> > > +				     "qcom,sm8550-ufshc",
> > > +				     "qcom,ufshc",
> > > +				     "jedec,ufs-2.0";
> > 
> > Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
> > driver.
> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead to
> dtbs_check failures. is it ok, if i continue with it ?

I was implying that you need to drop it from both binding and dts. It was
incorrect from the start anyway, so there is no ABI breakage. But make sure you
justify it in the description.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

[Pradeep Pragallapati]

On 1/6/2026 7:22 PM, Manivannan Sadhasivam wrote:
> On Tue, Jan 06, 2026 at 06:30:05PM +0530, Pradeep Pragallapati wrote:
>>
>>
>> On 1/6/2026 1:36 PM, Manivannan Sadhasivam wrote:
>>> On Mon, Jan 05, 2026 at 08:16:42PM +0530, Pradeep P V K wrote:
>>>> Add UFS host controller and PHY nodes for x1e80100 SoC.
>>>>
>>>
>>> Minor nits below. With those fixed,
>>>
>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>>>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
>>>>    1 file changed, 120 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> index f7d71793bc77..33899fa06aa4 100644
>>>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> @@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
>>>>    				 <0>,
>>>>    				 <0>,
>>>>    				 <0>,
>>>> -				 <0>,
>>>> -				 <0>,
>>>> -				 <0>;
>>>> +				 <&ufs_mem_phy 0>,
>>>> +				 <&ufs_mem_phy 1>,
>>>> +				 <&ufs_mem_phy 2>;
>>>>    			power-domains = <&rpmhpd RPMHPD_CX>;
>>>>    			#clock-cells = <1>;
>>>> @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
>>>>    			status = "disabled";
>>>>    		};
>>>> +		ufs_mem_phy: phy@1d80000 {
>>>> +			compatible = "qcom,x1e80100-qmp-ufs-phy",
>>>> +				     "qcom,sm8550-qmp-ufs-phy";
>>>> +			reg = <0x0 0x01d80000 0x0 0x2000>;
>>>> +
>>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>> +				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
>>>> +
>>>> +			clock-names = "ref",
>>>> +				      "ref_aux",
>>>> +				      "qref";
>>>> +			resets = <&ufs_mem_hc 0>;
>>>> +			reset-names = "ufsphy";
>>>> +
>>>> +			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
>>>> +
>>>> +			#clock-cells = <1>;
>>>> +			#phy-cells = <0>;
>>>> +
>>>> +			status = "disabled";
>>>> +		};
>>>> +
>>>> +		ufs_mem_hc: ufs@1d84000 {
>>>
>>> ufshc@
>> ok, i will update in the next patchset.
>>>
>>>> +			compatible = "qcom,x1e80100-ufshc",
>>>> +				     "qcom,sm8550-ufshc",
>>>> +				     "qcom,ufshc",
>>>> +				     "jedec,ufs-2.0";
>>>
>>> Drop jedec compatible as Qcom UFS controller cannot fallback to generic ufshc
>>> driver.
>> "jedec,ufs-2.0" was set to const in dt-bindings, dropping now will lead to
>> dtbs_check failures. is it ok, if i continue with it ?
> 
> I was implying that you need to drop it from both binding and dts. It was
> incorrect from the start anyway, so there is no ABI breakage. But make sure you
> justify it in the description.
> 
sure, i will update in my next patchset.

> - Mani
> 

Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC

[Bjorn Andersson]

On Tue, Jan 06, 2026 at 06:33:19PM +0530, Pradeep Pragallapati wrote:
> 
> 
> On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
> > On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
> > > Add UFSPHY, UFSHC compatible binding names and UFS devicetree
> > > enablement changes for Qualcomm x1e80100 SoC.
> > > 
> > > Changes in V3:
> > > - Update all dt-bindings commit messages with concise and informative
> > >    statements [Krzysztof]
> > > - keep the QMP UFS PHY order by last compatible in numerical ascending
> > >    order [Krzysztof]
> > > - Remove qcom,x1e80100-ufshc from select: enum: list of
> > >    qcom,sc7180-ufshc.yaml file [Krzysztof]
> > > - Update subject prefix for all dt-bindings [Krzysztof]
> > > - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
> > > - Add RB-by for board dts [Konrad]
> > > - Link to V2:
> > >    https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
> > 
> > Where did the previous changelog go?
> i missed to amend, i will update all changelog in my next patchset.

Please just adopt b4, go/upstream provides the documentation you need.

Regards,
Bjorn

> > 
> > > 
> > > ---
> > > Pradeep P V K (4):
> > >    dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
> > >      compatible
> > >    dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
> > >    arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
> > >    arm64: dts: qcom: hamoa-iot-evk: Enable UFS
> > > 
> > >   .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   4 +
> > >   .../bindings/ufs/qcom,sc7180-ufshc.yaml       |  37 +++---
> > >   arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts    |  18 +++
> > >   arch/arm64/boot/dts/qcom/hamoa.dtsi           | 123 +++++++++++++++++-
> > >   4 files changed, 164 insertions(+), 18 deletions(-)
> > > 
> > > -- 
> > > 2.34.1
> > > 
> > 
> 

Re: [PATCH V3 0/4] Add UFS support for x1e80100 SoC

[Pradeep Pragallapati]

On 1/6/2026 10:11 PM, Bjorn Andersson wrote:
> On Tue, Jan 06, 2026 at 06:33:19PM +0530, Pradeep Pragallapati wrote:
>>
>>
>> On 1/6/2026 3:50 AM, Dmitry Baryshkov wrote:
>>> On Mon, Jan 05, 2026 at 08:16:39PM +0530, Pradeep P V K wrote:
>>>> Add UFSPHY, UFSHC compatible binding names and UFS devicetree
>>>> enablement changes for Qualcomm x1e80100 SoC.
>>>>
>>>> Changes in V3:
>>>> - Update all dt-bindings commit messages with concise and informative
>>>>     statements [Krzysztof]
>>>> - keep the QMP UFS PHY order by last compatible in numerical ascending
>>>>     order [Krzysztof]
>>>> - Remove qcom,x1e80100-ufshc from select: enum: list of
>>>>     qcom,sc7180-ufshc.yaml file [Krzysztof]
>>>> - Update subject prefix for all dt-bindings [Krzysztof]
>>>> - Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
>>>> - Add RB-by for board dts [Konrad]
>>>> - Link to V2:
>>>>     https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
>>>
>>> Where did the previous changelog go?
>> i missed to amend, i will update all changelog in my next patchset.
> 
> Please just adopt b4, go/upstream provides the documentation you need.
sure, i will adopt to b4 going forward.
> 
> Regards,
> Bjorn
> 
>>>
>>>>
>>>> ---
>>>> Pradeep P V K (4):
>>>>     dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
>>>>       compatible
>>>>     dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
>>>>     arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
>>>>     arm64: dts: qcom: hamoa-iot-evk: Enable UFS
>>>>
>>>>    .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |   4 +
>>>>    .../bindings/ufs/qcom,sc7180-ufshc.yaml       |  37 +++---
>>>>    arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts    |  18 +++
>>>>    arch/arm64/boot/dts/qcom/hamoa.dtsi           | 123 +++++++++++++++++-
>>>>    4 files changed, 164 insertions(+), 18 deletions(-)
>>>>
>>>> -- 
>>>> 2.34.1
>>>>
>>>
>>