From: Matthias Brugger <mbrugger@suse.com>
To: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>,
Chester Lin <chester62515@gmail.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
NXP S32 Linux <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>
Subject: Re: [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
Date: Tue, 4 Feb 2025 23:01:18 +0100 [thread overview]
Message-ID: <68153618-d54a-4465-9fb2-a1232a8291d9@suse.com> (raw)
In-Reply-To: <20250113110512.506007-2-ciprianmarian.costea@oss.nxp.com>
On 13/01/2025 12:05, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add I2C[0..2] for S32G2 and S32G3 SoCs.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++
> 2 files changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..beae4d5cf54e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -333,6 +333,39 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -341,6 +374,28 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..79b38cd8b142 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -390,6 +390,42 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -398,6 +434,30 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
next prev parent reply other threads:[~2025-02-04 22:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
2025-01-15 15:28 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger [this message]
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
2025-02-04 15:20 ` Frank Li
2025-02-18 10:04 ` Shawn Guo
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