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[83.9.30.82]) by smtp.gmail.com with ESMTPSA id z8-20020a19f708000000b004f84d7706a7sm2276290lfe.7.2023.06.29.03.44.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jun 2023 03:45:01 -0700 (PDT) Message-ID: <6874227d-ea70-cae3-8267-1dd6baad997c@linaro.org> Date: Thu, 29 Jun 2023 12:44:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 2/4] regulator: Introduce Qualcomm REFGEN regulator driver Content-Language: en-US To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan , Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20230628-topic-refgen-v1-0-126e59573eeb@linaro.org> <20230628-topic-refgen-v1-2-126e59573eeb@linaro.org> <76e2f865-1a37-4517-b343-6aaea397fcf7@sirena.org.uk> <6109d966-b705-4e84-d8b3-c895ef540db3@linaro.org> From: Konrad Dybcio In-Reply-To: <6109d966-b705-4e84-d8b3-c895ef540db3@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29.06.2023 10:43, Konrad Dybcio wrote: > On 28.06.2023 21:28, Mark Brown wrote: >> On Wed, Jun 28, 2023 at 06:29:46PM +0200, Konrad Dybcio wrote: >> >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved. >>> + * Copyright (c) 2023, Linaro Limited >>> + */ >> >> Please use a C++ comment for the whole thing for consistency. > Oh that's new! > >> >>> +static int qcom_sdm845_refgen_enable(struct regulator_dev *rdev) >>> +{ >>> + struct qcom_refgen *vreg = rdev_get_drvdata(rdev); >>> + >>> + regmap_update_bits(vreg->base, REFGEN_REG_BG_CTRL, >>> + REFGEN_BG_CTRL_MASK, REFGEN_BG_CTRL_ENABLE); >>> + regmap_write(vreg->base, REFGEN_REG_BIAS_EN, REFGEN_BIAS_EN_ENABLE); >> >> For the enable and disable operations we use a mix of _update_bits() and >> absolute writes with no FIELD_PREP()... > This absolute write was accidentally fine as the mask began at bit0... > >> >>> +static int qcom_sdm845_refgen_is_enabled(struct regulator_dev *rdev) >>> +{ >>> + struct qcom_refgen *vreg = rdev_get_drvdata(rdev); >>> + u32 val; >>> + >>> + regmap_read(vreg->base, REFGEN_REG_BG_CTRL, &val); >>> + if (FIELD_GET(REFGEN_BG_CTRL_MASK, val) != REFGEN_BG_CTRL_ENABLE) >>> + return 0; >>> + >>> + regmap_read(vreg->base, REFGEN_REG_BIAS_EN, &val); >>> + if (FIELD_GET(REFGEN_BIAS_EN_MASK, val) != REFGEN_BIAS_EN_ENABLE) >>> + return 0; >> >> ...but when we read back the status we use FIELD_GET(). This looks like >> a bug, and given that one of the fields starts at bit 1 it presumably is >> one - FIELD_GET() will do shifting. > ...but a 2-bit-wide field will never equal 6. > Looks like I put unshifted values in the defines for REFGEN_BG_CTRL.. > > Thanks for spotting that! Even worse, I noticed I've been feeding a raw address into regmap functions.. :) Konrad > >> >>> +static int qcom_sm8250_refgen_enable(struct regulator_dev *rdev) >>> +{ >>> + struct qcom_refgen *vreg = rdev_get_drvdata(rdev); >>> + >>> + regmap_update_bits(vreg->base, REFGEN_REG_PWRDWN_CTRL5, >>> + REFGEN_PWRDWN_CTRL5_MASK, REFGEN_PWRDWN_CTRL5_ENABLE); >> >> This is a single bit in a single register so could use the standard >> helpers rather than open coding, the sdm845 does need custom operations >> due to having two fields to manage. > Forgot that's a thing! > > Konrad