From: Matthias Brugger <mbrugger@suse.com>
To: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>,
Chester Lin <chester62515@gmail.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
NXP S32 Linux <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>
Subject: Re: [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
Date: Tue, 4 Feb 2025 23:01:32 +0100 [thread overview]
Message-ID: <68d642bf-89e1-4cee-b0bc-86314ea10bbc@suse.com> (raw)
In-Reply-To: <20250113110512.506007-3-ciprianmarian.costea@oss.nxp.com>
On 13/01/2025 12:05, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
> RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
> file. Prepare to add other modules such as FlexCAN, DSPI easily in the
> future.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
> .../boot/dts/freescale/s32g399a-rdb3.dts | 1 +
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
> 5 files changed, 275 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index b9a119eea2b7..c4a195dd67bf 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-evb.dtsi"
>
> / {
> model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index aaa61a8ad0da..b5ba51696f43 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 828e353455b5..94f531be4017 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "s32g3.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> new file mode 100644
> index 000000000000..a44eff28073a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x101>, <0x111>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2352>, <0x2362>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x100>, <0x110>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + i2c1-grp0 {
> + pinmux = <0x131>, <0x141>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-grp1 {
> + pinmux = <0x2cd2>, <0x2ce2>;
> + };
> + };
> +
> + i2c1_gpio_pins: i2c1-gpio-pins {
> + i2c1-gpio-grp0 {
> + pinmux = <0x130>, <0x140>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-gpio-grp1 {
> + pinmux = <0x2cd0>, <0x2ce0>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> new file mode 100644
> index 000000000000..91fd8dbf2224
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x1f2>, <0x201>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2353>, <0x2363>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x1f0>, <0x200>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +
> + pcal6524: gpio-expander@22 {
> + compatible = "nxp,pcal6524";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
next prev parent reply other threads:[~2025-02-04 22:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
2025-01-15 15:28 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger [this message]
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
2025-02-04 15:20 ` Frank Li
2025-02-18 10:04 ` Shawn Guo
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