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[93.34.92.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4715520dd65sm137840795e9.15.2025.10.20.04.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:04:05 -0700 (PDT) Message-ID: <68f61725.050a0220.343129.f1f0@mx.google.com> X-Google-Original-Message-ID: Date: Mon, 20 Oct 2025 13:03:57 +0200 From: Christian Marangi To: Manivannan Sadhasivam Cc: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@airoha.com Subject: Re: [PATCH v5 5/5] PCI: mediatek: add support for Airoha AN7583 SoC References: <20251012205900.5948-1-ansuelsmth@gmail.com> <20251012205900.5948-6-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sun, Oct 19, 2025 at 01:01:44PM +0530, Manivannan Sadhasivam wrote: > On Sun, Oct 12, 2025 at 10:56:59PM +0200, Christian Marangi wrote: > > Add support for the second PCIe Root Complex present on Airoha AN7583 > > SoC. > > > > This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 > > also require workaround for the reset signals. > > > > Introduce a new flag to skip having to reset signals and also introduce > > some additional logic to configure the PBUS registers required for > > Airoha SoC. > > > > While at it, also add additional info on the PERST# Signal delay > > comments and use dedicated macro. > > > > This belongs to a separate patch which should come before this one. > > > Signed-off-by: Christian Marangi > > --- > > drivers/pci/controller/pcie-mediatek.c | 92 ++++++++++++++++++++------ > > 1 file changed, 70 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > > index 1678461e56d3..3340c005da4b 100644 > > --- a/drivers/pci/controller/pcie-mediatek.c > > +++ b/drivers/pci/controller/pcie-mediatek.c > > @@ -148,6 +148,7 @@ enum mtk_pcie_flags { > > NO_MSI = BIT(2), /* Bridge has no MSI support, and relies on an > > * external block > > */ > > + SKIP_PCIE_RSTB = BIT(3), /* Skip calling RSTB bits on PCIe probe */ > > }; > > > > /** > > @@ -684,28 +685,32 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > > regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > > } > > > > - /* Assert all reset signals */ > > - writel(0, port->base + PCIE_RST_CTRL); > > - > > - /* > > - * Enable PCIe link down reset, if link status changed from link up to > > - * link down, this will reset MAC control registers and configuration > > - * space. > > - */ > > - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > > - > > - /* > > - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > > - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > > - * be delayed 100ms (TPVPERL) for the power and clock to become stable. > > - */ > > - msleep(100); > > - > > - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > > - val = readl(port->base + PCIE_RST_CTRL); > > - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > > - PCIE_MAC_SRSTB | PCIE_CRSTB; > > - writel(val, port->base + PCIE_RST_CTRL); > > + if (!(soc->flags & SKIP_PCIE_RSTB)) { > > + /* Assert all reset signals */ > > + writel(0, port->base + PCIE_RST_CTRL); > > + > > + /* > > + * Enable PCIe link down reset, if link status changed from > > + * link up to link down, this will reset MAC control registers > > + * and configuration space. > > + */ > > + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > > + > > + /* > > + * Described in PCIe CEM specification revision 3.0 sections > > + * 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). > > + * > > + * The deassertion of PERST# should be delayed 100ms (TPVPERL) > > + * for the power and clock to become stable. > > You can drop the comments since PCIE_T_PVPERL_MS definition has them. > > > + */ > > + msleep(PCIE_T_PVPERL_MS); > > + > > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > > + val = readl(port->base + PCIE_RST_CTRL); > > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > > + PCIE_MAC_SRSTB | PCIE_CRSTB; > > + writel(val, port->base + PCIE_RST_CTRL); > > If PCIE_LINKDOWN_RST_EN corresponds to PERST# signal, then it should be > deasserted only after the power and REFCLK are stable. But I'm not sure what the > above PCIE_RST_CTRL setting is doing. If it somehow affects either power or > REFCLK, then it should come before PCIE_LINKDOWN_RST_EN. > Hi I checked MT7622 programming guide for this. The order of operation for reset is exactly what you have described. Indded, first everything is reset (assert all signals) then we set PCIE_LINKDOWN_RST_EN that in unrelated. We wait for clock stabilization with the msleep and only AFTER we deassert the PCIE_PERSTB. So no, PCIE_LINKDOWN_RST_EN is not PERST# signal sw but it's actually PCIE_PERSTB. > > -- > மணிவண்ணன் சதாசிவம் -- Ansuel