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Thu, 26 Mar 2026 05:56:09 -0700 (PDT) Message-ID: <693acd52-987e-4018-ae02-386dbd430462@tuxon.dev> Date: Thu, 26 Mar 2026 14:56:07 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] PCI: rzg3s-host: Add support for RZ/V2H(P) SoC To: "Lad, Prabhakar" Cc: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260318124450.163471-6-prabhakar.mahadev-lad.rj@bp.renesas.com> <605e8d4c-09e7-4d11-acdb-7829a85eacc3@tuxon.dev> Content-Language: en-US From: Claudiu Beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Prabhakar, On 3/25/26 13:53, Lad, Prabhakar wrote: >> from [1]: >> "For example, if rzg3s_pcie_resets_prepare_and_get() returns -EPROBE_DEFER, >> the static variable is never decremented. On subsequent probe retries, >> the variable will be artificially inflated, eventually causing the bounds >> check to fail and returning a permanent -EINVAL. This would also prevent >> driver unbind and rebind from working correctly." >> > The other alternative would be the below, where we wouldn't need to > use the num-lanes property but would need a comparison with the DT > compatible, Or move rzv2h_num_total_lanes outside of rzv2h_pcie_setup_lanes() and reset it on failure path. > > + for_each_compatible_node(np, NULL, "renesas,r9a09g057-pcie") { If it's possible I would avoid spreading compatibles though the file but instead use driver data where possible. Thank you, Claudiu > + if (of_device_is_available(np)) > + count++; > + } > + if (!count) > + return 0; > + > + /* If both PCIe channels are enabled configure the LINK_MASTER > in x2 lane mode. > + * If only one channel is enabled check the port index and if > port1 is enabled > + * configure the LINK_MASTER in x2 lane mode, otherwise keep > it in x4 lane mode. > + */ > + if (count == RZV2H_MAX_PCIE_PORTS || > + (count == 1 && host->channel == 1)) > + host->link_mode = RZV2H_PCIE_MODE_DUAL_X2; > + else > + host->link_mode = RZV2H_PCIE_MODE_SINGLE_X4;