From: Krzysztof Kozlowski <krzk@kernel.org>
To: Wenbin Yao <quic_wenbyao@quicinc.com>,
andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
will@kernel.org, quic_qianyu@quicinc.com, sfr@canb.auug.org.au,
linux-arm-kernel@lists.infradead.org,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: Re: [PATCH v1 1/3] arm64: defconfig: enable PCI Power Control for PCIe3
Date: Fri, 21 Mar 2025 08:36:53 +0100 [thread overview]
Message-ID: <694b6638-92b2-4ac0-a175-bd29aea6cba9@kernel.org> (raw)
In-Reply-To: <20250320055502.274849-2-quic_wenbyao@quicinc.com>
On 20/03/2025 06:55, Wenbin Yao wrote:
> From: Qiang Yu <quic_qianyu@quicinc.com>
>
> Enable the pwrctrl driver, which is utilized to manage the power supplies
> of the devices connected to the PCI slots. This ensures that the voltage
> rails of the x8 PCI slots on the X1E80100 - QCP can be correctly turned
> on/off if they are described under PCIe port device tree node.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 85ec2fba1..de86d1121 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -245,6 +245,7 @@ CONFIG_PCIE_LAYERSCAPE_GEN4=y
> CONFIG_PCI_ENDPOINT=y
> CONFIG_PCI_ENDPOINT_CONFIGFS=y
> CONFIG_PCI_EPF_TEST=m
> +CONFIG_PCI_PWRCTL_SLOT=y
Bartosz,
Wasn't the intention to select it the same way as PCI_PWRCTL_PWRSEQ is
selected?
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-21 7:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 5:54 [PATCH v1 0/3] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals config for PCIe3 Wenbin Yao
2025-03-20 5:55 ` [PATCH v1 1/3] arm64: defconfig: enable PCI Power Control " Wenbin Yao
2025-03-20 22:01 ` Bryan O'Donoghue
2025-03-24 6:55 ` Wenbin Yao (Consultant)
2025-03-21 7:36 ` Krzysztof Kozlowski [this message]
2025-03-21 9:43 ` Bartosz Golaszewski
2025-03-24 7:09 ` Wenbin Yao (Consultant)
2025-03-24 7:38 ` Krzysztof Kozlowski
2025-03-26 2:24 ` Wenbin Yao (Consultant)
2025-03-20 5:55 ` [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 Wenbin Yao
2025-03-20 22:06 ` Bryan O'Donoghue
2025-03-24 6:51 ` Wenbin Yao (Consultant)
2025-03-21 17:19 ` Dmitry Baryshkov
2025-03-24 7:11 ` Wenbin Yao (Consultant)
2025-03-20 5:55 ` [PATCH v1 3/3] arm64: dts: qcom: x1e80100-qcp: Add power control and sideband signals for PCIe3 Wenbin Yao
2025-03-20 22:08 ` Bryan O'Donoghue
2025-03-24 7:21 ` Wenbin Yao (Consultant)
2025-03-21 7:39 ` Krzysztof Kozlowski
2025-03-24 7:13 ` Wenbin Yao (Consultant)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=694b6638-92b2-4ac0-a175-bd29aea6cba9@kernel.org \
--to=krzk@kernel.org \
--cc=andersson@kernel.org \
--cc=bartosz.golaszewski@linaro.org \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=quic_qianyu@quicinc.com \
--cc=quic_wenbyao@quicinc.com \
--cc=robh@kernel.org \
--cc=sfr@canb.auug.org.au \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).