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Wed, 09 Sep 2026 03:39:30 -0700 (PDT) X-Received: by 2002:a17:90b:3d89:b0:398:dcfe:968e with SMTP id 98e67ed59e1d1-39bac3f9063mr7705565a91.20.1788950370145; Wed, 09 Sep 2026 03:39:30 -0700 (PDT) Received: from [10.218.7.34] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3397c13dfb1sm6400531eec.2.2026.09.09.03.39.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Sep 2026 03:39:29 -0700 (PDT) Message-ID: <695dfc01-2c1f-4503-9049-2ae266774ed2@oss.qualcomm.com> Date: Wed, 9 Sep 2026 16:09:20 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/7] arm64: dts: qcom: glymur: Add ADC support for Glymur CRD To: Konrad Dybcio , Jonathan Cameron , David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> <20260731-pmic5_gen4_adc-v1-6-9c49b2eea6f9@oss.qualcomm.com> <52c023c0-a61f-4116-851f-ed19de4d23f2@oss.qualcomm.com> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <52c023c0-a61f-4116-851f-ed19de4d23f2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: rPBVdPw6ELTAThfy8sVLrtZT0-3muDMX X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDExOCBTYWx0ZWRfXxvA/Acbg+B1v 2tZ7BOLXdeCP8cMtat7N8Vmh9XTQ/OBcK4kB54vLQg0jwJdLtayDJTxJyuhhZ378kJH0UyWvbC7 SvdlqOUzIGh7wZyto2boqyTH7iXmCE0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDExOCBTYWx0ZWRfX5FwpDtNHmMzK CsnLyBzIrLEMYJy95ikPDwPjPTnoXaIx7ey0TV5muNFAxq37/wKPQuOKNs1ddOPkgyDpOUKgFZY R7WNRoj5X/xmyDWOISqK1gf5pCQ/7cQxlzGbGQJjwpIDrvW/4nloRlRzEG5cMnSYA9vAPql8xqk +Dhl0QJ6M1UWPQVPRfmWjONDgYQ2xI9q49v5olzzhgaZIQf7KZss6BzjQAlQ9KjN+kSenKXMYLx /irXd/2KP831taMe1lVupDfmGXFJAz2lCJRLAFSN94lRxt5XMNEBuy1swpMv9+Bq9Gpwu2i1qTp jlALVERjxmrtVdlEMMUB2Sa9JkQFWqhrNz0MuUCtAZtDkmB9iu0RqXLvq29uznd8bMdrUnjWmny zUHsRoUo1/eXisHNrALRKQFFSqN34DAqMndzmfPIuyvCaAcwbrNkONPxtITSRTLfe1gXS4dZRA4 6/MkUiV0SdG4tinMQ3Q== X-Authority-Analysis: v=2.4 cv=S+jpBosP c=1 sm=1 tr=0 ts=6aa13763 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=MEGDCpZww2ShHeW_oQkA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: rPBVdPw6ELTAThfy8sVLrtZT0-3muDMX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090118 Hi Konrad, On 9/3/2026 2:19 PM, Konrad Dybcio wrote: > On 7/31/26 8:06 PM, Jishnu Prakash wrote: >> Add the ADC channels under the PMK8850 ADC node for the >> other PMICS on the board with ADC peripherals. This includes >> die temperature and VPH power channels per PMIC. > > [...] > >> + thermal-zones { >> + sys-0-thermal { > > Please name it xo-therm or something similar to make the connection > more obvious Sure, I'll update the node name to "xo-thermal" and make similar changes in the other patch too. > > [...] > >> +&pmcx0102_c_e0_temp_alarm { >> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 2)>; >> + io-channel-names = "thermal"; >> +}; >> + >> +&pmcx0102_c_e1_temp_alarm { >> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 2)>; >> + io-channel-names = "thermal"; >> +}; >> + >> +&pmcx0102_d_e0_temp_alarm { >> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>; >> + io-channel-names = "thermal"; >> +}; >> + >> +&pmcx0102_d_e1_temp_alarm { >> + io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 3)>; >> + io-channel-names = "thermal"; >> +}; > > Are these going to be always wired up this way on all Glymur boards? I'm not sure what you mean here - each temp-alarm peripheral here is using the die_temp channel from the ADC on the same PMIC to read the PMIC die temperature. Die_temp is an internal sensor and the die_temp ADC channel is always present on any PMIC which has ADC, it is not like thermistors which are optionally connected to AMUX/GPIO pins and can change between boards, so I think we can consider the above configuration will not change between Glymur boards. Does this answer your question? Checking some more, I noticed that this file (glymur-crd.dtsi) is included in one other board file (mahua-crd.dts) and that board lacks a few PMICs used on Glymur, so I'll also make sure to delete any Glymur ADC channels absent for that board. Thanks, JIshnu > > Konrad