[PATCH v4 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[PATCH v4 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Michal Simek]

All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
MicroBlaze V (RISC-V ISA) that's why move boards description from arm
folder to soc folder.
Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings:
soc: renesas: Move renesas.yaml from arm to soc").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---

Changes in v4:
- s/chagne/change/ in commit message
- Fix binding location

Changes in v3:
- Fix commit message reported by Krzysztof and add his ACK

Changes in v2:
- New patch in the series

Based on discussion here.
https://lore.kernel.org/r/20231108-copper-scoff-b4de5febb954@spud

---
 .../devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml         | 2 +-
 MAINTAINERS                                                     | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)
 rename Documentation/devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml (98%)

diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
similarity index 98%
rename from Documentation/devicetree/bindings/arm/xilinx.yaml
rename to Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index f57ed0347894..95758deca325 100644
--- a/Documentation/devicetree/bindings/arm/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/xilinx.yaml#
+$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Xilinx Zynq Platforms
diff --git a/MAINTAINERS b/MAINTAINERS
index ea790149af79..14ad00009a63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3020,6 +3020,7 @@ F:	Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
 F:	Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
 F:	Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
 F:	Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
+F:	Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
 F:	Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
 F:	arch/arm/mach-zynq/
 F:	drivers/clocksource/timer-cadence-ttc.c
-- 
2.36.1

[PATCH v4 2/2] dt-bindings: soc: Add new board description for MicroBlaze V

[Michal Simek]

MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor. Processor can
be used with standard AMD/Xilinx IPs including interrupt controller and
timer.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---

Changes in v4:
- Fix indentation reported by bot

Changes in v3:
- Add Krzysztof's ACK

Changes in v2:
- Put MicroBlaze V description to xilinx.yaml
- Add qemu target platform as platform used for testing.

 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index 95758deca325..d4c0fe1fe435 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -132,6 +132,11 @@ properties:
           - const: xlnx,zynqmp-smk-k26
           - const: xlnx,zynqmp
 
+      - description: AMD MicroBlaze V (QEMU)
+        items:
+          - const: qemu,mbv
+          - const: amd,mbv
+
 additionalProperties: true
 
 ...
-- 
2.36.1

Re: [PATCH v4 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Michal Simek]

On 11/23/23 08:02, Michal Simek wrote:
> All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
> MicroBlaze V (RISC-V ISA) that's why move boards description from arm
> folder to soc folder.
> Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings:
> soc: renesas: Move renesas.yaml from arm to soc").
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> 
> Changes in v4:
> - s/chagne/change/ in commit message
> - Fix binding location
> 
> Changes in v3:
> - Fix commit message reported by Krzysztof and add his ACK
> 
> Changes in v2:
> - New patch in the series
> 
> Based on discussion here.
> https://lore.kernel.org/r/20231108-copper-scoff-b4de5febb954@spud
> 
> ---
>   .../devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml         | 2 +-
>   MAINTAINERS                                                     | 1 +
>   2 files changed, 2 insertions(+), 1 deletion(-)
>   rename Documentation/devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml (98%)
> 
> diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> similarity index 98%
> rename from Documentation/devicetree/bindings/arm/xilinx.yaml
> rename to Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> index f57ed0347894..95758deca325 100644
> --- a/Documentation/devicetree/bindings/arm/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> @@ -1,7 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/arm/xilinx.yaml#
> +$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
>   title: Xilinx Zynq Platforms
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ea790149af79..14ad00009a63 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3020,6 +3020,7 @@ F:	Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
>   F:	Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
>   F:	Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
>   F:	Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
> +F:	Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>   F:	Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
>   F:	arch/arm/mach-zynq/
>   F:	drivers/clocksource/timer-cadence-ttc.c


Applied.
M

Re: [PATCH v4 2/2] dt-bindings: soc: Add new board description for MicroBlaze V

[Michal Simek]

On 11/23/23 08:02, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor. Processor can
> be used with standard AMD/Xilinx IPs including interrupt controller and
> timer.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> 
> Changes in v4:
> - Fix indentation reported by bot
> 
> Changes in v3:
> - Add Krzysztof's ACK
> 
> Changes in v2:
> - Put MicroBlaze V description to xilinx.yaml
> - Add qemu target platform as platform used for testing.
> 
>   Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> index 95758deca325..d4c0fe1fe435 100644
> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> @@ -132,6 +132,11 @@ properties:
>             - const: xlnx,zynqmp-smk-k26
>             - const: xlnx,zynqmp
>   
> +      - description: AMD MicroBlaze V (QEMU)
> +        items:
> +          - const: qemu,mbv
> +          - const: amd,mbv
> +
>   additionalProperties: true
>   
>   ...

Applied.
M