[PATCH 1/2] dt-bindings: crypto: eip93: add clock gate and reset line

[PATCH 1/2] dt-bindings: crypto: eip93: add clock gate and reset line

[Aleksander Jan Bajkowski]

Add the clock gate and reset line, both of which are available
on the Airoha AN7581. Both properties are optional.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 .../crypto/inside-secure,safexcel-eip93.yaml         | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
index 997bf9717f9e..058454b679b4 100644
--- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
+++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
@@ -48,6 +48,12 @@ properties:
   interrupts:
     maxItems: 1
 
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -57,11 +63,17 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/en7523-clk.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/reset/airoha,en7581-reset.h>
 
     crypto@1e004000 {
       compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
       reg = <0x1fb70000 0x1000>;
 
+      clocks = <&scuclk EN7523_CLK_CRYPTO>;
+
       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+
+      resets = <&scuclk EN7581_CRYPTO_RST>;
     };
-- 
2.47.3

[PATCH 2/2] arm64: dts: airoha: en7581: add crypto offload support

[Aleksander Jan Bajkowski]

Add support for the built-in cryptographic accelerator. This accelerator
supports 3DES, AES (128/192/256 bit), ARC4, MD5, SHA1, SHA224, and SHA256.
It also supports full IPSEC, SRTP and TLS offload.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index ff6908a76e8e..4931b704235a 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -300,6 +300,18 @@ rng@1faa1000 {
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		crypto@1e004000 {
+			compatible = "airoha,en7581-eip93",
+				"inside-secure,safexcel-eip93ies";
+			reg = <0x0 0x1fb70000 0x0 0x1000>;
+
+			clocks = <&scuclk EN7523_CLK_CRYPTO>;
+
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+
+			resets = <&scuclk EN7581_CRYPTO_RST>;
+		};
+
 		system-controller@1fbf0200 {
 			compatible = "airoha,en7581-gpio-sysctl", "syscon",
 				     "simple-mfd";
-- 
2.47.3

Re: [PATCH 2/2] arm64: dts: airoha: en7581: add crypto offload support

[Christian Marangi]

On Tue, Mar 03, 2026 at 08:39:18PM +0100, Aleksander Jan Bajkowski wrote:
> Add support for the built-in cryptographic accelerator. This accelerator
> supports 3DES, AES (128/192/256 bit), ARC4, MD5, SHA1, SHA224, and SHA256.
> It also supports full IPSEC, SRTP and TLS offload.
> 
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> ---
>  arch/arm64/boot/dts/airoha/en7581.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index ff6908a76e8e..4931b704235a 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -300,6 +300,18 @@ rng@1faa1000 {
>  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		crypto@1e004000 {
> +			compatible = "airoha,en7581-eip93",
> +				"inside-secure,safexcel-eip93ies";
> +			reg = <0x0 0x1fb70000 0x0 0x1000>;
> +
> +			clocks = <&scuclk EN7523_CLK_CRYPTO>;
> +
> +			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			resets = <&scuclk EN7581_CRYPTO_RST>;

I guess you can drop the extra new line between clocks interrupts and resets.

Does the driver supports these property tho? For example the clock is just
enabled or tweaked to a specific frequency? Same question for resets.

> +		};
> +
>  		system-controller@1fbf0200 {
>  			compatible = "airoha,en7581-gpio-sysctl", "syscon",
>  				     "simple-mfd";
> -- 
> 2.47.3
> 

-- 
	Ansuel

Re: [PATCH 2/2] arm64: dts: airoha: en7581: add crypto offload support

[Aleksander Jan Bajkowski]

Hi Christian,

On 3/3/26 21:00, Christian Marangi wrote:
> On Tue, Mar 03, 2026 at 08:39:18PM +0100, Aleksander Jan Bajkowski wrote:
>> Add support for the built-in cryptographic accelerator. This accelerator
>> supports 3DES, AES (128/192/256 bit), ARC4, MD5, SHA1, SHA224, and SHA256.
>> It also supports full IPSEC, SRTP and TLS offload.
>>
>> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
>> ---
>>   arch/arm64/boot/dts/airoha/en7581.dtsi | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
>> index ff6908a76e8e..4931b704235a 100644
>> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
>> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
>> @@ -300,6 +300,18 @@ rng@1faa1000 {
>>   			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>>   		};
>>   
>> +		crypto@1e004000 {
>> +			compatible = "airoha,en7581-eip93",
>> +				"inside-secure,safexcel-eip93ies";
>> +			reg = <0x0 0x1fb70000 0x0 0x1000>;
>> +
>> +			clocks = <&scuclk EN7523_CLK_CRYPTO>;
>> +
>> +			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			resets = <&scuclk EN7581_CRYPTO_RST>;
> I guess you can drop the extra new line between clocks interrupts and resets.

It makes sense.

>
> Does the driver supports these property tho? For example the clock is just
> enabled or tweaked to a specific frequency? Same question for resets.

As far as I know, the driver doesn't use these properties. They may be used
in the future.

>
>> +		};
>> +
>>   		system-controller@1fbf0200 {
>>   			compatible = "airoha,en7581-gpio-sysctl", "syscon",
>>   				     "simple-mfd";
>> -- 
>> 2.47.3
>>

Re: [PATCH 1/2] dt-bindings: crypto: eip93: add clock gate and reset line

[Conor Dooley]

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On Tue, Mar 03, 2026 at 08:39:17PM +0100, Aleksander Jan Bajkowski wrote:
> Add the clock gate and reset line, both of which are available
> on the Airoha AN7581. Both properties are optional.

Why are they optional?

> 
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> ---
>  .../crypto/inside-secure,safexcel-eip93.yaml         | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> index 997bf9717f9e..058454b679b4 100644
> --- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> @@ -48,6 +48,12 @@ properties:
>    interrupts:
>      maxItems: 1
>  
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
>  required:
>    - compatible
>    - reg
> @@ -57,11 +63,17 @@ additionalProperties: false
>  
>  examples:
>    - |
> +    #include <dt-bindings/clock/en7523-clk.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/airoha,en7581-reset.h>
>  
>      crypto@1e004000 {
>        compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
>        reg = <0x1fb70000 0x1000>;
>  
> +      clocks = <&scuclk EN7523_CLK_CRYPTO>;
> +
>        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +
> +      resets = <&scuclk EN7581_CRYPTO_RST>;
>      };
> -- 
> 2.47.3
> 

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Re: [PATCH 1/2] dt-bindings: crypto: eip93: add clock gate and reset line

[Aleksander Jan Bajkowski]

Hi Conor,

On 3/4/26 20:08, Conor Dooley wrote:
> On Tue, Mar 03, 2026 at 08:39:17PM +0100, Aleksander Jan Bajkowski wrote:
>> Add the clock gate and reset line, both of which are available
>> on the Airoha AN7581. Both properties are optional.
> Why are they optional?

No reason. In theory, a hardware designer could connect the reset
to a fixed input signal. In practice, all SoCs on the market have
a built-in reset and clock controller. I can mark them as required
in the next revision.

>> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
>> ---
>>   .../crypto/inside-secure,safexcel-eip93.yaml         | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>> index 997bf9717f9e..058454b679b4 100644
>> --- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>> +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>> @@ -48,6 +48,12 @@ properties:
>>     interrupts:
>>       maxItems: 1
>>   
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  resets:
>> +    maxItems: 1
>> +
>>   required:
>>     - compatible
>>     - reg
>> @@ -57,11 +63,17 @@ additionalProperties: false
>>   
>>   examples:
>>     - |
>> +    #include <dt-bindings/clock/en7523-clk.h>
>>       #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/reset/airoha,en7581-reset.h>
>>   
>>       crypto@1e004000 {
>>         compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
>>         reg = <0x1fb70000 0x1000>;
>>   
>> +      clocks = <&scuclk EN7523_CLK_CRYPTO>;
>> +
>>         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +      resets = <&scuclk EN7581_CRYPTO_RST>;
>>       };
>> -- 
>> 2.47.3
>>
Best regards,
Aleksander

Re: [PATCH 1/2] dt-bindings: crypto: eip93: add clock gate and reset line

[Conor Dooley]

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On Wed, Mar 04, 2026 at 10:46:41PM +0100, Aleksander Jan Bajkowski wrote:
> Hi Conor,
> 
> On 3/4/26 20:08, Conor Dooley wrote:
> > On Tue, Mar 03, 2026 at 08:39:17PM +0100, Aleksander Jan Bajkowski wrote:
> > > Add the clock gate and reset line, both of which are available
> > > on the Airoha AN7581. Both properties are optional.
> > Why are they optional?
> 
> No reason. In theory, a hardware designer could connect the reset
> to a fixed input signal. In practice, all SoCs on the market have
> a built-in reset and clock controller. I can mark them as required
> in the next revision.

Right, the reset could be optional on some systems, but sounds like it
is always there on the an7581. The clock is probably mandatory always.
I think you should make it required in the binding, but not in the
driver since that needs to work with existing devicetrees.
Technically this is an ABI break (new required property), so at least
mention in the commit message that you're aware of this.


> 
> > > Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> > > ---
> > >   .../crypto/inside-secure,safexcel-eip93.yaml         | 12 ++++++++++++
> > >   1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> > > index 997bf9717f9e..058454b679b4 100644
> > > --- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> > > +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
> > > @@ -48,6 +48,12 @@ properties:
> > >     interrupts:
> > >       maxItems: 1
> > > +  clocks:
> > > +    maxItems: 1
> > > +
> > > +  resets:
> > > +    maxItems: 1
> > > +
> > >   required:
> > >     - compatible
> > >     - reg
> > > @@ -57,11 +63,17 @@ additionalProperties: false
> > >   examples:
> > >     - |
> > > +    #include <dt-bindings/clock/en7523-clk.h>
> > >       #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +    #include <dt-bindings/reset/airoha,en7581-reset.h>
> > >       crypto@1e004000 {
> > >         compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
> > >         reg = <0x1fb70000 0x1000>;
> > > +      clocks = <&scuclk EN7523_CLK_CRYPTO>;
> > > +
> > >         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > > +
> > > +      resets = <&scuclk EN7581_CRYPTO_RST>;
> > >       };
> > > -- 
> > > 2.47.3
> > > 
> Best regards,
> Aleksander
> 
> 

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