[PATCH v4 0/3] mmc: dw_mmc: Support optional BIU clock

[PATCH v4 0/3] mmc: dw_mmc: Support optional BIU clock

[ping.gao]

From: Ping Gao <ping.gao@samsung.com>

This series relaxes the BIU clock constraint in the dt-bindings and
updates the dw_mmc driver to treat it as optional. This is necessary
for SoC designs where BIU and CIU share a single clock source.

The entire series is resent as v4 to fix previous threading issues and
address feedback on the YAML schema and commit formatting.

v4:
 - Resend as a new standalone thread to fix the threading mess.
 - dt-bindings: sync clock-names with clocks using oneOf.
 - dt-bindings: remove redundant description text.
 - Update commit messages with hardware-level justification.
 - Fix Signed-off-by name format and missing blank lines.

Ping Gao (3):
  dt-bindings: mmc: synopsys-dw-mshc: relax clocks constraint
  mmc: dw_mmc-k3: before set biu_clk rate, check biu_clk available or
    not
  mmc: dw_mmc: Using devm_clk_get_optional() for biu_clk

 .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml   | 13 +++++++++----
 drivers/mmc/host/dw_mmc-k3.c                        |  5 +++++
 drivers/mmc/host/dw_mmc.c                           |  2 +-
 3 files changed, 15 insertions(+), 5 deletions(-)

-- 
2.50.1

[PATCH v4 1/3] dt-bindings: mmc: synopsys-dw-mshc: relax clocks constraint

[ping.gao]

From: Ping Gao <ping.gao@samsung.com>

In some SoC designs (e.g., certain Samsung Exynos platforms), the Bus
Interface Unit (BIU) and Card Interface Unit (CIU) clocks are tied
together or driven by a single clock source. In such hardware
configurations, only one clock entry needs to be described in the
device tree.

Relax the clocks and clock-names constraints to allow a single clock
while maintaining backward compatibility for existing dual-clock
designs.

Signed-off-by: Ping Gao <ping.gao@samsung.com>
---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml   | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index a6292777e376..47dff8d4be27 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -24,16 +24,21 @@ properties:
     maxItems: 1
 
   clocks:
-    minItems: 2
+    minItems: 1
     maxItems: 2
     description:
       Handle to "biu" and "ciu" clocks for the
       bus interface unit clock and the card interface unit clock.
 
   clock-names:
-    items:
-      - const: biu
-      - const: ciu
+    minItems: 1
+    maxItems: 2
+    oneOf:
+      - items:
+          - const: biu
+          - const: ciu
+      - items:
+          - const: ciu
 
   iommus:
     maxItems: 1
-- 
2.50.1

[PATCH v4 2/3] mmc: dw_mmc-k3: before set biu_clk rate, check biu_clk available or not

[ping.gao]

From: Ping Gao <ping.gao@samsung.com>

If biu_clk is not available, no need to try to set and get
rate of it, just bail out and print a warning

Signed-off-by: Ping Gao <ping.gao@samsung.com>
---
 drivers/mmc/host/dw_mmc-k3.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index ad6aa1aea549..ccb6bfe3e0ce 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -190,6 +190,11 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 	int ret;
 	unsigned int clock;
 
+	if (IS_ERR_OR_NULL(host->biu_clk)) {
+		dev_err(host->dev, "biu_clk not available\n");
+		return;
+	}
+
 	clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
 
 	ret = clk_set_rate(host->biu_clk, clock);
-- 
2.50.1

[PATCH v4 3/3] mmc: dw_mmc: Using devm_clk_get_optional() for biu_clk

[ping.gao]

From: Ping Gao <ping.gao@samsung.com>

By using devm_clk_get_optional, if clk is optional for device and not define in dts
it will return NULL, then clk_prepare_enable/clk_disable_unprepare for biu_clk is safe to
bail out internally.

before biu_clk in dwmmc driver devm_clk_get fail, but it's ERR_PTR,
not null,it will panic when call clk_prepare
log is below:
[7:   binder:436_2: 4998] Unable to handle kernel paging request at virtual address fffffffffffffffe
[7:   binder:436_2: 4998] Mem abort info:
[7:   binder:436_2: 4998]   ESR = 0x0000000096000005
[7:   binder:436_2: 4998]   EC = 0x25: DABT (current EL), IL = 32 bits
[7:   binder:436_2: 4998]   SET = 0, FnV = 0
[7:   binder:436_2: 4998]   EA = 0, S1PTW = 0
[7:   binder:436_2: 4998]   FSC = 0x05: level 1 translation fault
...
[7:   binder:436_2: 4998] Call trace:
[7:   binder:436_2: 4998]  clk_prepare+0x10/0x24
[7:   binder:436_2: 4998]  dw_mci_runtime_resume+0x50/0x2d8 [dw_mmc_samsung cd210e210975263404c28fc89778f369f8398f0c]
[7:   binder:436_2: 4998]  dw_mci_exynos_runtime_resume+0x18/0x58 [dw_mmc_exynos_samsung 2735a594c7c9c9e8c65b0b87523fbf70dcaabfff]
[7:   binder:436_2: 4998]  pm_generic_runtime_resume+0x40/0x58
[7:   binder:436_2: 4998]  pm_runtime_force_resume+0x9c/0x134
[7:   binder:436_2: 4998]  platform_pm_resume+0x40/0x8c
[7:   binder:436_2: 4998]  dpm_run_callback+0x64/0x230
[7:   binder:436_2: 4998]  __device_resume+0x1d8/0x394
[7:   binder:436_2: 4998]  dpm_resume+0x110/0x2b8
[7:   binder:436_2: 4998]  dpm_resume_end+0x1c/0x38
[7:   binder:436_2: 4998]  suspend_devices_and_enter+0x828/0xab0
[7:   binder:436_2: 4998]  pm_suspend+0x334/0x618
[7:   binder:436_2: 4998]  state_store+0x104/0x144
[7:   binder:436_2: 4998]  kobj_attr_store+0x30/0x48
[7:   binder:436_2: 4998]  sysfs_kf_write+0x54/0x6c
[7:   binder:436_2: 4998]  kernfs_fop_write_iter+0x104/0x1a8
[7:   binder:436_2: 4998]  vfs_write+0x24c/0x2f4
[7:   binder:436_2: 4998]  ksys_write+0x78/0xe8
[7:   binder:436_2: 4998]  __arm64_sys_write+0x1c/0x2c
[7:   binder:436_2: 4998]  invoke_syscall+0x58/0x114
[7:   binder:436_2: 4998]  el0_svc_common+0xac/0xe0
[7:   binder:436_2: 4998]  do_el0_svc+0x1c/0x28
[7:   binder:436_2: 4998]  el0_svc+0x38/0x68
[7:   binder:436_2: 4998]  el0t_64_sync_handler+0x68/0xbc
[7:   binder:436_2: 4998]  el0t_64_sync+0x1a8/0x1ac

Signed-off-by: Ping Gao <ping.gao@samsung.com>
---
 drivers/mmc/host/dw_mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index c5db92bbb094..6bcc1e7233c0 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -3375,7 +3375,7 @@ int dw_mci_probe(struct dw_mci *host)
 					     "platform data not available\n");
 	}
 
-	host->biu_clk = devm_clk_get(host->dev, "biu");
+	host->biu_clk = devm_clk_get_optional(host->dev, "biu");
 	if (IS_ERR(host->biu_clk)) {
 		dev_dbg(host->dev, "biu clock not available\n");
 		ret = PTR_ERR(host->biu_clk);
-- 
2.50.1

Re: [PATCH v4 1/3] dt-bindings: mmc: synopsys-dw-mshc: relax clocks constraint

[Krzysztof Kozlowski]

On 28/02/2026 07:24, ping.gao wrote:
> From: Ping Gao <ping.gao@samsung.com>
> 
> In some SoC designs (e.g., certain Samsung Exynos platforms), the Bus
> Interface Unit (BIU) and Card Interface Unit (CIU) clocks are tied

Again, no.

Read and respond to previous feedback. It's like third version where you
did not do it...

Samsung Exynos platforms have all two clocks. Look at the sources.


Best regards,
Krzysztof

Re: [PATCH v4 3/3] mmc: dw_mmc: Using devm_clk_get_optional() for biu_clk

[Krzysztof Kozlowski]

On 28/02/2026 07:24, ping.gao wrote:
> From: Ping Gao <ping.gao@samsung.com>
> 
> By using devm_clk_get_optional, if clk is optional for device and not define in dts
> it will return NULL, then clk_prepare_enable/clk_disable_unprepare for biu_clk is safe to
> bail out internally.
> 
> before biu_clk in dwmmc driver devm_clk_get fail, but it's ERR_PTR,
> not null,it will panic when call clk_prepare
> log is below:
> [7:   binder:436_2: 4998] Unable to handle kernel paging request at virtual address fffffffffffffffe
> [7:   binder:436_2: 4998] Mem abort info:
> [7:   binder:436_2: 4998]   ESR = 0x0000000096000005
> [7:   binder:436_2: 4998]   EC = 0x25: DABT (current EL), IL = 32 bits
> [7:   binder:436_2: 4998]   SET = 0, FnV = 0
> [7:   binder:436_2: 4998]   EA = 0, S1PTW = 0
> [7:   binder:436_2: 4998]   FSC = 0x05: level 1 translation fault


No, we don't support here your downstream kernel.

Start working on upstream instead, please.

Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: synopsys-dw-mshc: relax clocks constraint

[Krzysztof Kozlowski]

On Sat, Feb 28, 2026 at 10:44:03AM +0100, Krzysztof Kozlowski wrote:
> On 28/02/2026 07:24, ping.gao wrote:
> > From: Ping Gao <ping.gao@samsung.com>
> > 
> > In some SoC designs (e.g., certain Samsung Exynos platforms), the Bus
> > Interface Unit (BIU) and Card Interface Unit (CIU) clocks are tied
> 
> Again, no.
> 
> Read and respond to previous feedback. It's like third version where you
> did not do it...
> 
> Samsung Exynos platforms have all two clocks. Look at the sources.

And to clarify before you respond "but my downstream Exynos 999999 has
one clock": downstream does not exist. We don't care about it. I advise
to fix your downstream if that's the problem you are having.

If you keep sending the same for sixth time without responding to
feedback, I might get inpatient and NAK it without giving arguments,
because I already feel like this is wasting my time.

Best regards,
Krzysztof

Re: [PATCH v4 1/3] dt-bindings: mmc: synopsys-dw-mshc: relax clocks constraint

[ping.gao]

On Sat, Feb 28, 2026 at 10:44:03AM +0100, Krzysztof Kozlowski wrote:
> On 28/02/2026 07:24, ping.gao wrote:
> > From: Ping Gao <ping.gao@samsung.com>
> > 
> > In some SoC designs (e.g., certain Samsung Exynos platforms), the Bus
> > Interface Unit (BIU) and Card Interface Unit (CIU) clocks are tied
> 
> Again, no.
> 
> Read and respond to previous feedback. It's like third version where you
> did not do it...
> 
> Samsung Exynos platforms have all two clocks. Look at the sources.

Hi Krzysztof,

I apologise for repeatedly submitting patches that did not address your feedback on the
Exynos clock architecture. My earlier patches assumed that some Exynos platforms
use a single clock, while, as you correctly pointed out, all Exynos SoCs expose both a
BIU (Bus Interface Unit) and a CIU (Card Interface Unit) clock.

I regret the oversight and the extra time it has taken you to point this out several
times. 

I appreciate your patience and the guidance you have provided. 

Thank you for your time and understanding.

Best regards,
Ping Gao