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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6656f306csm913017466b.61.2024.12.13.07.07.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2024 07:07:02 -0800 (PST) Message-ID: <69dffe54-939d-47c3-b951-4a4dea11eae0@oss.qualcomm.com> Date: Fri, 13 Dec 2024 16:06:59 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes To: Manikanta Mylavarapu , bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com References: <20241213134950.234946-1-quic_mmanikan@quicinc.com> <20241213134950.234946-4-quic_mmanikan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241213134950.234946-4-quic_mmanikan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: _aaI6ASxYYoPu0qPnQfu7ZMkijNSbr7n X-Proofpoint-GUID: _aaI6ASxYYoPu0qPnQfu7ZMkijNSbr7n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130107 On 13.12.2024 2:49 PM, Manikanta Mylavarapu wrote: > Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices > found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3 > host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. > > Signed-off-by: Manikanta Mylavarapu > --- > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 482 +++++++++++++++++++++++++- > 1 file changed, 477 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > index 5e219f900412..ade512bcb180 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > / { > @@ -143,7 +144,99 @@ soc@0 { > compatible = "simple-bus"; > #address-cells = <2>; > #size-cells = <2>; > - ranges = <0 0 0 0 0x10 0>; > + ranges = <0 0 0 0 0x0 0xffffffff>; This must be a separate change, with a clear explanation > + > + pcie0_phy: phy@84000 { > + compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", > + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > + reg = <0 0x00084000 0 0x2000>; > + clocks = <&gcc GCC_PCIE0_AUX_CLK>, > + <&gcc GCC_PCIE0_AHB_CLK>, > + <&gcc GCC_PCIE0_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; > + assigned-clock-rates = <20000000>; > + > + resets = <&gcc GCC_PCIE0_PHY_BCR>, > + <&gcc GCC_PCIE0PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie0_pipe_clk_src"; > + > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + pcie1_phy: phy@8c000 { > + compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", > + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > + reg = <0 0x0008c000 0 0x2000>; > + clocks = <&gcc GCC_PCIE1_AUX_CLK>, > + <&gcc GCC_PCIE1_AHB_CLK>, > + <&gcc GCC_PCIE1_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; > + assigned-clock-rates = <20000000>; > + > + resets = <&gcc GCC_PCIE1_PHY_BCR>, > + <&gcc GCC_PCIE1PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie1_pipe_clk_src"; > + > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + pcie2_phy: phy@f4000 { > + compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", > + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; > + reg = <0 0x000f4000 0 0x2000>; > + clocks = <&gcc GCC_PCIE2_AUX_CLK>, > + <&gcc GCC_PCIE2_AHB_CLK>, > + <&gcc GCC_PCIE2_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; > + assigned-clock-rates = <20000000>; > + > + resets = <&gcc GCC_PCIE2_PHY_BCR>, > + <&gcc GCC_PCIE2PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie2_pipe_clk_src"; > + > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + pcie3_phy: phy@fc000 { > + compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", > + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; > + reg = <0 0x000fc000 0 0x2000>; > + clocks = <&gcc GCC_PCIE3_AUX_CLK>, > + <&gcc GCC_PCIE3_AHB_CLK>, > + <&gcc GCC_PCIE3_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; > + assigned-clock-rates = <20000000>; > + > + resets = <&gcc GCC_PCIE3_PHY_BCR>, > + <&gcc GCC_PCIE3PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie3_pipe_clk_src"; > + > + #phy-cells = <0>; > + status = "disabled"; > + }; > > tlmm: pinctrl@1000000 { > compatible = "qcom,ipq5424-tlmm"; > @@ -168,11 +261,11 @@ gcc: clock-controller@1800000 { > reg = <0 0x01800000 0 0x40000>; > clocks = <&xo_board>, > <&sleep_clk>, > + <&pcie0_phy>, > + <&pcie1_phy>, > <0>, This leftover zero needs to be removed too, currently the wrong clocks are used as parents > - <0>, > - <0>, > - <0>, > - <0>; > + <&pcie2_phy>, > + <&pcie3_phy>; > #clock-cells = <1>; > #reset-cells = <1>; > #interconnect-cells = <1>; > @@ -292,6 +385,385 @@ frame@f42d000 { > }; > }; > > + pcie3: pcie@40000000 { > + compatible = "qcom,pcie-ipq5424", > + "qcom,pcie-ipq9574"; > + reg = <0 0x40000000 0 0xf1d>, > + <0 0x40000f20 0 0xa8>, > + <0 0x40001000 0 0x1000>, > + <0 0x000f8000 0 0x3000>, > + <0 0x40100000 0 0x1000>; > + reg-names = "dbi", "elbi", "atu", "parf", "config"; Please make this a vertical list, in all nodes [...] > + phys = <&pcie3_phy>; > + phy-names = "pciephy"; > + interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, > + <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + status = "disabled"; And add a newline above status Konrad