From: Dmitry Osipenko <digetx@gmail.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Laxman Dewangan <ldewangan@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Vinod Koul <vinod.koul@intel.com>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
dmaengine@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
Date: Wed, 27 Sep 2017 15:12:50 +0300 [thread overview]
Message-ID: <69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4@gmail.com> (raw)
In-Reply-To: <0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com>
On 27.09.2017 11:34, Jon Hunter wrote:
>
> On 27/09/17 02:57, Dmitry Osipenko wrote:
>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>
>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>> on Tegra20/30 SoC's.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++
>>>> 1 file changed, 23 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> new file mode 100644
>>>> index 000000000000..2af9aa76ae11
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> @@ -0,0 +1,23 @@
>>>> +* NVIDIA Tegra AHB DMA controller
>>>> +
>>>> +Required properties:
>>>> +- compatible: Must be "nvidia,tegra20-ahbdma"
>>>> +- reg: Should contain registers base address and length.
>>>> +- interrupts: Should contain one entry, DMA controller interrupt.
>>>> +- clocks: Should contain one entry, DMA controller clock.
>>>> +- resets : Should contain one entry, DMA controller reset.
>>>> +- #dma-cells: Should be <1>. The cell represents DMA request select value
>>>> + for the peripheral. For more details consult the Tegra TRM's
>>>> + documentation, in particular AHB DMA channel control register
>>>> + REQ_SEL field.
>>>
>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>
>>
>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>> software to decide what trigger to select. So it shouldn't be in the binding.
>
> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>
GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers
are software-defined, so that software could create transfer chains.
>> And I think the same applies to requester... any objections?
>
> Well, the REQ_SEL should definitely be in the binding.
>
Okay.
> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
> like we never bothered with it for the APB DMA and so maybe no ones uses
> this.
>
--
Dmitry
next prev parent reply other threads:[~2017-09-27 12:12 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-25 23:22 [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver Dmitry Osipenko
2017-09-25 23:22 ` [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry Dmitry Osipenko
2017-09-26 9:56 ` Peter De Schrijver
2017-09-26 14:46 ` Dmitry Osipenko
2017-09-27 8:36 ` Peter De Schrijver
2017-09-27 9:41 ` Dmitry Osipenko
2017-09-25 23:22 ` [PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20 Dmitry Osipenko
2017-09-26 10:01 ` Peter De Schrijver
2017-09-25 23:22 ` [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller Dmitry Osipenko
2017-09-26 14:45 ` Jon Hunter
[not found] ` <481add20-9cea-a91a-e72c-45a824362e64-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-26 16:06 ` Dmitry Osipenko
2017-09-26 21:37 ` Jon Hunter
[not found] ` <8fa6108d-421d-8054-c05c-9681a0e25518-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-26 23:00 ` Dmitry Osipenko
2017-09-28 9:29 ` Vinod Koul
2017-09-28 12:17 ` Dmitry Osipenko
2017-09-28 14:06 ` Dmitry Osipenko
2017-09-28 14:35 ` Dmitry Osipenko
[not found] ` <260fa409-0d07-ec9e-9e3b-fb08255026d8-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-28 16:22 ` Vinod Koul
2017-09-28 16:37 ` Dmitry Osipenko
2017-09-28 16:21 ` Vinod Koul
[not found] ` <cover.1506380746.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-25 23:22 ` [PATCH v1 3/5] dt-bindings: Add DT bindings " Dmitry Osipenko
2017-09-26 14:50 ` Jon Hunter
2017-09-26 15:16 ` Dmitry Osipenko
[not found] ` <bee2a524-0891-01e1-4e03-f6cf6a89e6b1-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-27 1:57 ` Dmitry Osipenko
2017-09-27 8:34 ` Jon Hunter
2017-09-27 12:12 ` Dmitry Osipenko [this message]
[not found] ` <69ea8dec-db7a-fcfa-6fa7-ea70de4c9ef4-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-27 13:44 ` Jon Hunter
2017-09-27 13:46 ` Jon Hunter
[not found] ` <432fff47-6750-08c4-a91d-1a5d154245bc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-27 14:29 ` Dmitry Osipenko
2017-09-27 23:32 ` Stephen Boyd
2017-09-28 8:33 ` Jon Hunter
[not found] ` <0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-29 19:30 ` Stephen Warren
2017-09-30 3:11 ` Dmitry Osipenko
2017-10-02 17:05 ` Stephen Warren
2017-10-02 23:02 ` Dmitry Osipenko
2017-10-03 10:32 ` Jon Hunter
[not found] ` <4443a8fb-7a4d-922b-2dd3-53236d39a050-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-03 12:07 ` Dmitry Osipenko
2017-10-03 12:19 ` Jon Hunter
2017-10-03 15:38 ` Stephen Warren
2017-10-03 17:04 ` Dmitry Osipenko
[not found] ` <604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-10-05 20:33 ` Rob Herring
2017-10-05 21:30 ` Dmitry Osipenko
2017-09-25 23:22 ` [PATCH v1 5/5] ARM: dts: tegra: Add AHB DMA controller nodes Dmitry Osipenko
2017-09-28 9:31 ` [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver Vinod Koul
2017-09-28 12:24 ` Dmitry Osipenko
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