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[79.22.5.99]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4903caede9fsm9490145e9.14.2026.05.21.01.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 01:22:29 -0700 (PDT) Message-ID: <6a0ec0c5.16c38fd9.2b754a.4dc3@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 21 May 2026 10:22:27 +0200 From: Christian Marangi To: Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Lorenzo Bianconi , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v8 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY References: <20260520150912.11614-1-ansuelsmth@gmail.com> <20260520150912.11614-3-ansuelsmth@gmail.com> <20260521-ambrosial-abiding-lyrebird-9dc86f@quoll> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260521-ambrosial-abiding-lyrebird-9dc86f@quoll> On Thu, May 21, 2026 at 09:44:16AM +0200, Krzysztof Kozlowski wrote: > On Wed, May 20, 2026 at 05:09:07PM +0200, Christian Marangi wrote: > > Add documentation for Airoha AN7581 USB PHY that describe the USB PHY > > for the USB controller. > > > > Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is > > always supported. The USB 3.0 mode is optional and depends on the Serdes > > mode currently configured on the system for the relevant USB port. > > > > To correctly calibrate, the USB 2.0 port require correct value in > > "airoha,usb2-monitor-clk-sel" property. Both the 2 USB 2.0 port permit > > selecting one of the 4 monitor clock for calibration (internal clock not > > exposed to the system) but each port have only one of the 4 actually > > connected in HW hence the correct value needs to be specified in DT > > based on board and the physical port. Normally it's monitor clock 1 for > > USB1 and monitor clock 2 for USB2. > > > > To correctly setup the Serdes mode attached to the USB 3.0 mode, a phys > > property is required with the phandle pointing to the correct Serdes port > > provided by the SCU node. > > > ^^^ here - required but: > I think I have to rephrase it. It's required if the USB3 is used/wanted. In the other case for the USB2 phy is not needed. I will bettet describe this in commit description and on the phys property description. > > + phys: > > + items: > > + - description: phandle to Serdes PHY > > + > > + '#phy-cells': > > + description: The cell contains the mode, PHY_TYPE_USB2 or PHY_TYPE_USB3, > > + as defined in dt-bindings/phy/phy.h. > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - airoha,usb2-monitor-clk-sel > > 'phys' is not required? I think you need it to configure the serdes > correctly, no? > > > + - '#phy-cells' > > + > > +additionalProperties: false > > Best regards, > Krzysztof > -- Ansuel