From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vidya Sagar Subject: Re: [PATCH V7 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Date: Tue, 21 May 2019 23:47:45 +0530 Message-ID: <6a2c0a9a-1c37-3e32-535a-aaf0db2f101d@nvidia.com> References: <20190517123846.3708-1-vidyas@nvidia.com> <20190517123846.3708-13-vidyas@nvidia.com> <20190521105455.GK29166@ulmo> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190521105455.GK29166@ulmo> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Thierry Reding Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com List-Id: devicetree@vger.kernel.org On 5/21/2019 4:24 PM, Thierry Reding wrote: > On Fri, May 17, 2019 at 06:08:43PM +0530, Vidya Sagar wrote: >> Enable PCIe controller nodes to enable respective PCIe slots on >> P2972-0000 board. Following is the ownership of slots by different >> PCIe controllers. >> Controller-0 : M.2 Key-M slot >> Controller-1 : On-board Marvell eSATA controller >> Controller-3 : M.2 Key-E slot >> >> Signed-off-by: Vidya Sagar >> --- >> Changes since [v6]: >> * None >> >> Changes since [v5]: >> * Arranged PCIe nodes in the order of their addresses >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * Changed P2U label names to reflect new format that includes 'hsio'/'nvhs' >> strings to reflect UPHY brick they belong to >> >> Changes since [v1]: >> * Dropped 'pcie-' from phy-names property strings >> >> .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- >> .../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +++++++++++++++++++ >> 2 files changed, 42 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi >> index 0fd5bd29fbf9..30a83d4c5b69 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi >> @@ -191,7 +191,7 @@ >> regulator-boot-on; >> }; >> >> - sd3 { >> + vdd_1v8ao: sd3 { >> regulator-name = "VDD_1V8AO"; >> regulator-min-microvolt = <1800000>; >> regulator-max-microvolt = <1800000>; >> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts >> index 73801b48d1d8..a22704e76a84 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts >> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts >> @@ -167,4 +167,45 @@ >> }; >> }; >> }; >> + >> + pcie@14100000 { >> + status = "okay"; >> + >> + vddio-pex-ctl-supply = <&vdd_1v8ao>; >> + >> + phys = <&p2u_hsio_0>; >> + phy-names = "p2u-0"; >> + }; >> + >> + pcie@14140000 { >> + status = "okay"; >> + >> + vddio-pex-ctl-supply = <&vdd_1v8ao>; >> + >> + phys = <&p2u_hsio_7>; >> + phy-names = "p2u-0"; >> + }; >> + >> + pcie@14180000 { >> + status = "okay"; >> + >> + vddio-pex-ctl-supply = <&vdd_1v8ao>; >> + >> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, >> + <&p2u_hsio_5>; >> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; >> + }; >> + >> + pcie@141a0000 { >> + status = "disabled"; >> + >> + vddio-pex-ctl-supply = <&vdd_1v8ao>; >> + >> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, >> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, >> + <&p2u_nvhs_6>, <&p2u_nvhs_7>; >> + >> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", >> + "p2u-5", "p2u-6", "p2u-7"; >> + }; > > This last controller is disabled by default. Why do we need to include > all of this if it's not going to be used anyway? I want to keep this entry ready by populating all the required fields. When pinctrl driver is ready, I'll send out patches to enable this node as well. > > Thierry >