From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: bhelgaas@google.com, konrad.dybcio@linaro.org,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1
Date: Mon, 19 Dec 2022 23:46:03 +0200 [thread overview]
Message-ID: <6a59addb-b1a0-8536-c909-25c4c4447e09@linaro.org> (raw)
In-Reply-To: <20221219191427.480085-4-manivannan.sadhasivam@linaro.org>
On 19/12/2022 21:14, Manivannan Sadhasivam wrote:
> Both PCIe0 and PCIe1 controllers are capable of receiving MSIs from
> endpoint devices using GIC-ITS MSI controller. Add support for it.
>
> Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the
> msi-map-mask of 0xff00, all the 32 devices under these two busses can
> share the same Device ID.
>
> The GIC-ITS MSI implementation provides an advantage over internal MSI
> implementation using Locality-specific Peripheral Interrupts (LPI) that
> would allow MSIs to be targeted for each CPU core.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 570475040d95..276ceba4c247 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -1733,9 +1733,9 @@ pcie0: pci@1c00000 {
> ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
>
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> - #interrupt-cells = <1>;
> + msi-map = <0x0 &gic_its 0x5980 0x1>,
> + <0x100 &gic_its 0x5981 0x1>;
Does ITS support handling more than one MSI interrupt per device?
Otherwise it might be better to switch to multi-MSI scheme using SPI
interrupts.
> + msi-map-mask = <0xff00>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> @@ -1842,9 +1842,9 @@ pcie1: pci@1c08000 {
> ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
> <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> - #interrupt-cells = <1>;
> + msi-map = <0x0 &gic_its 0x5a01 0x1>,
> + <0x100 &gic_its 0x5a00 0x1>;
Are you sure that the order is correct here?
> + msi-map-mask = <0xff00>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-12-19 21:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-19 19:14 [PATCH 0/3] Qcom: Add GIC-ITS support to SM8450 PCIe controllers Manivannan Sadhasivam
2022-12-19 19:14 ` [PATCH 1/3] dt-bindings: PCI: qcom: Update maintainers Manivannan Sadhasivam
2022-12-20 10:24 ` Krzysztof Kozlowski
2022-12-19 19:14 ` [PATCH 2/3] dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties Manivannan Sadhasivam
2022-12-20 10:29 ` Krzysztof Kozlowski
2022-12-19 19:14 ` [PATCH 3/3] arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1 Manivannan Sadhasivam
2022-12-19 20:51 ` Konrad Dybcio
2022-12-20 10:42 ` Manivannan Sadhasivam
2022-12-19 21:46 ` Dmitry Baryshkov [this message]
2022-12-20 10:34 ` Manivannan Sadhasivam
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