From mboxrd@z Thu Jan  1 00:00:00 1970
From: Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: Re: [PATCH v2 3/5] drm/bridge/synopsys: Add MIPI DSI host controller
 bridge
Date: Thu, 25 May 2017 16:53:01 +0530
Message-ID: <6a5d9b38-0b74-3442-f6f3-a1f42c7e705c@codeaurora.org>
References: <1495207218-11372-1-git-send-email-philippe.cornu@st.com>
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To: Philippe CORNU <philippe.cornu-qxv4g6HH51o@public.gmane.org>, Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, David Airlie <airlied-cv59FeDIM0c@public.gmane.org>, Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>, Benjamin Gaignard <benjamin.gaignard-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Yannick Fertre <yannick.fertre-qxv4g6HH51o@public.gmane.org>, Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>, Eric Anholt <eric-WhKQ6XTQaPysTnJN9+BGXg@public.gmane.org>, Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, xinliang.liu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, zourongrong-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Xinwei Kong <kong.kongxinwei-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>, Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Fabien Dessenne <fabien.dessenne-qxv4g6HH51o@public.gmane.org>, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Mickael Reulier <mickael.reulier-qxv4g6HH51o@public.gmane.org>, Vincent Abriou <vincent.abriou-qxv4g6HH51o@public.gmane.org>, Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>, Ludovic Barre <ludovic.barre-qxv4g6HH51o@public.gmane.org>, Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
List-Id: devicetree@vger.kernel.org

Hi Philippe,

Thanks a lot for creating a bridge driver for this.

Copying some Hisilicon and Rockchip folks so that they can consider adapting to this.

Some comments below.

On 05/19/2017 08:50 PM, Philippe CORNU wrote:
> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>
> Signed-off-by: Philippe CORNU <philippe.cornu-qxv4g6HH51o@public.gmane.org>
> ---
>  drivers/gpu/drm/bridge/synopsys/Kconfig       |    9 +
>  drivers/gpu/drm/bridge/synopsys/Makefile      |    2 +
>  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 1024 +++++++++++++++++++++++++
>  3 files changed, 1035 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
> index 40d2827..d7fbdff 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
> @@ -21,3 +21,12 @@ config DRM_DW_HDMI_I2S_AUDIO
>  	help
>  	  Support the I2S Audio interface which is part of the Synopsys
>  	  Designware HDMI block.
> +
> +config DRM_DW_MIPI_DSI
> +	tristate "Synopsys DesignWare MIPI DSI host controller bridge"
> +	select DRM_KMS_HELPER
> +	select DRM_MIPI_DSI
> +	select DRM_PANEL
> +	help
> +	  Choose this if you want to use the Synopsys DesignWare MIPI DSI host
> +	  controller bridge.
> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile
> index 17aa7a6..5f57d36 100644
> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
> @@ -3,3 +3,5 @@
>  obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>  obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>  obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
> +
> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> new file mode 100644
> index 0000000..041f564
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -0,0 +1,1024 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Modified by Philippe Cornu <philippe.cornu-qxv4g6HH51o@public.gmane.org>
> + * This generic Synopsys Designware MIPI DSI host driver is based on the
> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <video/mipi_display.h>
> +
> +#define DSI_VERSION			0x00
> +#define DSI_PWR_UP			0x04
> +#define RESET				0
> +#define POWERUP				BIT(0)
> +
> +#define DSI_CLKMGR_CFG			0x08
> +#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
> +#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
> +
> +#define DSI_DPI_VCID			0x0c
> +#define DPI_VID(vid)			(((vid) & 0x3) << 0)
> +
> +#define DSI_DPI_COLOR_CODING		0x10
> +#define EN18_LOOSELY			BIT(8)
> +#define DPI_COLOR_CODING_16BIT_1	0x0
> +#define DPI_COLOR_CODING_16BIT_2	0x1
> +#define DPI_COLOR_CODING_16BIT_3	0x2
> +#define DPI_COLOR_CODING_18BIT_1	0x3
> +#define DPI_COLOR_CODING_18BIT_2	0x4
> +#define DPI_COLOR_CODING_24BIT		0x5
> +
> +#define DSI_DPI_CFG_POL			0x14
> +#define COLORM_ACTIVE_LOW		BIT(4)
> +#define SHUTD_ACTIVE_LOW		BIT(3)
> +#define HSYNC_ACTIVE_LOW		BIT(2)
> +#define VSYNC_ACTIVE_LOW		BIT(1)
> +#define DATAEN_ACTIVE_LOW		BIT(0)
> +
> +#define DSI_DPI_LP_CMD_TIM		0x18
> +#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
> +#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
> +
> +#define DSI_DBI_CFG			0x20
> +#define DSI_DBI_CMDSIZE			0x28
> +
> +#define DSI_PCKHDL_CFG			0x2c
> +#define EN_CRC_RX			BIT(4)
> +#define EN_ECC_RX			BIT(3)
> +#define EN_BTA				BIT(2)
> +#define EN_EOTP_RX			BIT(1)
> +#define EN_EOTP_TX			BIT(0)
> +
> +#define DSI_MODE_CFG			0x34
> +#define ENABLE_VIDEO_MODE		0
> +#define ENABLE_CMD_MODE			BIT(0)
> +
> +#define DSI_VID_MODE_CFG		0x38
> +#define FRAME_BTA_ACK			BIT(14)
> +#define ENABLE_LOW_POWER		(0x3f << 8)
> +#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
> +#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
> +#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
> +#define VID_MODE_TYPE_BURST			0x2
> +#define VID_MODE_TYPE_MASK			0x3
> +
> +#define DSI_VID_PKT_SIZE		0x3c
> +#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
> +#define VID_PKT_MAX_SIZE		0x3fff
> +
> +#define DSI_VID_HSA_TIME		0x48
> +#define DSI_VID_HBP_TIME		0x4c
> +#define DSI_VID_HLINE_TIME		0x50
> +#define DSI_VID_VSA_LINES		0x54
> +#define DSI_VID_VBP_LINES		0x58
> +#define DSI_VID_VFP_LINES		0x5c
> +#define DSI_VID_VACTIVE_LINES		0x60
> +#define DSI_CMD_MODE_CFG		0x68
> +#define MAX_RD_PKT_SIZE_LP		BIT(24)
> +#define DCS_LW_TX_LP			BIT(19)
> +#define DCS_SR_0P_TX_LP			BIT(18)
> +#define DCS_SW_1P_TX_LP			BIT(17)
> +#define DCS_SW_0P_TX_LP			BIT(16)
> +#define GEN_LW_TX_LP			BIT(14)
> +#define GEN_SR_2P_TX_LP			BIT(13)
> +#define GEN_SR_1P_TX_LP			BIT(12)
> +#define GEN_SR_0P_TX_LP			BIT(11)
> +#define GEN_SW_2P_TX_LP			BIT(10)
> +#define GEN_SW_1P_TX_LP			BIT(9)
> +#define GEN_SW_0P_TX_LP			BIT(8)
> +#define EN_ACK_RQST			BIT(1)
> +#define EN_TEAR_FX			BIT(0)
> +
> +#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
> +					 DCS_LW_TX_LP | \
> +					 DCS_SR_0P_TX_LP | \
> +					 DCS_SW_1P_TX_LP | \
> +					 DCS_SW_0P_TX_LP | \
> +					 GEN_LW_TX_LP | \
> +					 GEN_SR_2P_TX_LP | \
> +					 GEN_SR_1P_TX_LP | \
> +					 GEN_SR_0P_TX_LP | \
> +					 GEN_SW_2P_TX_LP | \
> +					 GEN_SW_1P_TX_LP | \
> +					 GEN_SW_0P_TX_LP)
> +
> +#define DSI_GEN_HDR			0x6c
> +#define GEN_HDATA(data)			(((data) & 0xffff) << 8)
> +#define GEN_HDATA_MASK			(0xffff << 8)
> +#define GEN_HTYPE(type)			(((type) & 0xff) << 0)
> +#define GEN_HTYPE_MASK			0xff
> +
> +#define DSI_GEN_PLD_DATA		0x70
> +
> +#define DSI_CMD_PKT_STATUS		0x74
> +#define GEN_CMD_EMPTY			BIT(0)
> +#define GEN_CMD_FULL			BIT(1)
> +#define GEN_PLD_W_EMPTY			BIT(2)
> +#define GEN_PLD_W_FULL			BIT(3)
> +#define GEN_PLD_R_EMPTY			BIT(4)
> +#define GEN_PLD_R_FULL			BIT(5)
> +#define GEN_RD_CMD_BUSY			BIT(6)
> +
> +#define DSI_TO_CNT_CFG			0x78
> +#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
> +#define LPRX_TO_CNT(p)			((p) & 0xffff)
> +
> +#define DSI_BTA_TO_CNT			0x8c
> +#define DSI_LPCLK_CTRL			0x94
> +#define AUTO_CLKLANE_CTRL		BIT(1)
> +#define PHY_TXREQUESTCLKHS		BIT(0)
> +
> +#define DSI_PHY_TMR_LPCLK_CFG		0x98
> +#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
> +#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
> +
> +#define DSI_PHY_TMR_CFG			0x9c
> +#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
> +#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
> +#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
> +
> +#define DSI_PHY_RSTZ			0xa0
> +#define PHY_DISFORCEPLL			0
> +#define PHY_ENFORCEPLL			BIT(3)
> +#define PHY_DISABLECLK			0
> +#define PHY_ENABLECLK			BIT(2)
> +#define PHY_RSTZ			0
> +#define PHY_UNRSTZ			BIT(1)
> +#define PHY_SHUTDOWNZ			0
> +#define PHY_UNSHUTDOWNZ			BIT(0)
> +
> +#define DSI_PHY_IF_CFG			0xa4
> +#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
> +#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
> +
> +#define DSI_PHY_STATUS			0xb0
> +#define LOCK				BIT(0)
> +#define STOP_STATE_CLK_LANE		BIT(2)
> +
> +#define DSI_PHY_TST_CTRL0		0xb4
> +#define PHY_TESTCLK			BIT(1)
> +#define PHY_UNTESTCLK			0
> +#define PHY_TESTCLR			BIT(0)
> +#define PHY_UNTESTCLR			0
> +
> +#define DSI_PHY_TST_CTRL1		0xb8
> +#define PHY_TESTEN			BIT(16)
> +#define PHY_UNTESTEN			0
> +#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
> +#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
> +
> +#define DSI_INT_ST0			0xbc
> +#define DSI_INT_ST1			0xc0
> +#define DSI_INT_MSK0			0xc4
> +#define DSI_INT_MSK1			0xc8
> +
> +#define PHY_STATUS_TIMEOUT_US		10000
> +#define CMD_PKT_STATUS_TIMEOUT_US	20000
> +
> +struct dw_mipi_dsi {
> +	struct drm_bridge bridge;
> +	struct drm_connector connector;
> +	struct mipi_dsi_host dsi_host;
> +	struct drm_panel *panel;
> +	struct device *dev;
> +	void __iomem *base;
> +
> +	struct clk *pllref_clk;
> +	struct clk *pclk;
> +
> +	int dpms_mode;
> +	unsigned int lane_mbps; /* per lane */
> +	u32 channel;
> +	u32 lanes;
> +	u32 format;
> +	unsigned long mode_flags;
> +
> +	const struct dw_mipi_dsi_plat_data *plat_data;
> +};
> +
> +enum dw_mipi_dsi_mode {
> +	DW_MIPI_DSI_CMD_MODE,
> +	DW_MIPI_DSI_VID_MODE,
> +};

This seems a bit unnecessary, we already have this info in the DSI device's
mode_flags field.

> +
> +/*
> + * The controller should generate 2 frames before
> + * preparing the peripheral.
> + */
> +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
> +{
> +	int refresh, two_frames;
> +
> +	refresh = drm_mode_vrefresh(mode);
> +	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
> +	msleep(two_frames);
> +}
> +
> +static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
> +{
> +	return container_of(host, struct dw_mipi_dsi, dsi_host);
> +}
> +
> +static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
> +{
> +	return container_of(con, struct dw_mipi_dsi, connector);
> +}
> +
> +static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
> +{
> +	return container_of(bridge, struct dw_mipi_dsi, bridge);
> +}
> +
> +static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> +{
> +	writel_relaxed(val, dsi->base + reg);
> +}
> +
> +static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> +{
> +	return readl_relaxed(dsi->base + reg);
> +}
> +
> +static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +
> +	if (device->lanes > dsi->plat_data->max_data_lanes) {
> +		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
> +			device->lanes);
> +		return -EINVAL;
> +	}
> +
> +	dsi->lanes = device->lanes;
> +	dsi->channel = device->channel;
> +	dsi->format = device->format;
> +	dsi->mode_flags = device->mode_flags;
> +	dsi->panel = of_drm_find_panel(device->dev.of_node);
> +	if (dsi->panel)
> +		return drm_panel_attach(dsi->panel, &dsi->connector);
> +
> +	return -EINVAL;
> +}
> +
> +static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
> +				   struct mipi_dsi_device *device)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +
> +	drm_panel_detach(dsi->panel);
> +
> +	return 0;
> +}
> +
> +static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> +				   const struct mipi_dsi_msg *msg)
> +{
> +	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
> +	u32 val = 0;
> +
> +	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> +		val |= EN_ACK_RQST;
> +	if (lpm)
> +		val |= CMD_MODE_ALL_LP;
> +
> +	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> +
> +	/* todo debug force the PHY_TXREQUESTCLKHS, to be improved... */

Will this break rockchip driver if they adapt to it?

If so, can you make this part of dw_mipi_dsi_plat_data, and mention it as
a quirk for STM?

> +	dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +
> +	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> +}
> +
> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> +{
> +	int ret;
> +	u32 val, mask;
> +
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, !(val & GEN_CMD_FULL), 1000,
> +				 CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to get available command FIFO\n");
> +		return ret;
> +	}
> +
> +	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> +
> +	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +				 val, (val & mask) == mask,
> +				 1000, CMD_PKT_STATUS_TIMEOUT_US);
> +	if (ret < 0) {
> +		dev_err(dsi->dev, "failed to write command FIFO\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
> +				       const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	u16 data = 0;
> +	u32 val;
> +
> +	if (msg->tx_len > 0)
> +		data |= tx_buf[0];
> +	if (msg->tx_len > 1)
> +		data |= tx_buf[1] << 8;
> +
> +	if (msg->tx_len > 2) {
> +		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> +}
> +
> +static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> +				      const struct mipi_dsi_msg *msg)
> +{
> +	const u8 *tx_buf = msg->tx_buf;
> +	int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
> +	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> +	u32 remainder;
> +	u32 val;
> +
> +	if (msg->tx_len < 3) {
> +		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
> +			msg->tx_len);
> +		return -EINVAL;
> +	}
> +
> +	while (DIV_ROUND_UP(len, pld_data_bytes)) {
> +		if (len < pld_data_bytes) {
> +			remainder = 0;
> +			memcpy(&remainder, tx_buf, len);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			len = 0;
> +		} else {
> +			memcpy(&remainder, tx_buf, pld_data_bytes);
> +			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
> +			tx_buf += pld_data_bytes;
> +			len -= pld_data_bytes;
> +		}
> +
> +		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> +					 val, !(val & GEN_PLD_W_FULL), 1000,
> +					 CMD_PKT_STATUS_TIMEOUT_US);
> +		if (ret < 0) {
> +			dev_err(dsi->dev,
> +				"failed to get available write payload FIFO\n");
> +			return ret;
> +		}
> +	}
> +
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
> +}
> +
> +static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
> +					 const struct mipi_dsi_msg *msg)
> +{
> +	struct dw_mipi_dsi *dsi = host_to_dsi(host);
> +	int ret;
> +
> +	/*
> +	 * todo dw drv improvements

could you write the TODOs in caps so that we don't miss them?

> +	 * use mipi_dsi_create_packet() instead of all following
> +	 * functions and code (no switch cases, no
> +	 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
> +	 * and use packet.header...

Is there something missing in the mipi_dsi helpers to do this now? Or we're
just leaving this for later?

> +	 */
> +	dw_mipi_message_config(dsi, msg);
> +
> +	switch (msg->type) {
> +	case MIPI_DSI_DCS_SHORT_WRITE:
> +	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> +	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> +		ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
> +		break;
> +	case MIPI_DSI_DCS_LONG_WRITE:
> +		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
> +		break;
> +	default:
> +		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
> +			msg->type);
> +		ret = -EINVAL;
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
> +	.attach = dw_mipi_dsi_host_attach,
> +	.detach = dw_mipi_dsi_host_detach,
> +	.transfer = dw_mipi_dsi_host_transfer,
> +};
> +
> +static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	u32 val;
> +
> +	/*
> +	 * todo dw drv improvements
> +	 * enabling low power is panel-dependent, we should use the
> +	 * panel configuration here...
> +	 */
> +	val = ENABLE_LOW_POWER;
> +
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> +		val |= VID_MODE_TYPE_BURST;
> +	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> +	else
> +		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> +
> +	dsi_write(dsi, DSI_VID_MODE_CFG, val);
> +}
> +
> +static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> +				 enum dw_mipi_dsi_mode mode)
> +{
> +	if (mode == DW_MIPI_DSI_CMD_MODE) {
> +		dsi_write(dsi, DSI_PWR_UP, RESET);
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +		dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +	} else {
> +		dsi_write(dsi, DSI_PWR_UP, RESET);
> +		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> +		dw_mipi_dsi_video_mode_config(dsi);
> +		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +		dsi_write(dsi, DSI_PWR_UP, POWERUP);
> +	}
> +}
> +
> +static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> +}
> +
> +static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * The maximum permitted escape clock is 20MHz and it is derived from
> +	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
> +	 *
> +	 *     (lane_mbps >> 3) / esc_clk_division < 20
> +	 * which is:
> +	 *     (lane_mbps >> 3) / 20 > esc_clk_division
> +	 */
> +	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> +
> +	dsi_write(dsi, DSI_PWR_UP, RESET);
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> +		  | PHY_RSTZ | PHY_SHUTDOWNZ);
> +	/*
> +	 * todo dw drv improvements
> +	 * timeout clock division should be computed with the
> +	 * high speed transmission counter timeout and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> +		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
> +}
> +
> +static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> +				   struct drm_display_mode *mode)
> +{
> +	u32 val = 0, color = 0;
> +
> +	switch (dsi->format) {
> +	case MIPI_DSI_FMT_RGB888:
> +		color = DPI_COLOR_CODING_24BIT;
> +		break;
> +	case MIPI_DSI_FMT_RGB666:
> +		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
> +		break;
> +	case MIPI_DSI_FMT_RGB666_PACKED:
> +		color = DPI_COLOR_CODING_18BIT_1;
> +		break;
> +	case MIPI_DSI_FMT_RGB565:
> +		color = DPI_COLOR_CODING_16BIT_1;
> +		break;
> +	}
> +
> +	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> +		val |= VSYNC_ACTIVE_LOW;
> +	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> +		val |= HSYNC_ACTIVE_LOW;
> +
> +	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
> +	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> +	dsi_write(dsi, DSI_DPI_CFG_POL, val);
> +	/*
> +	 * todo dw drv improvements
> +	 * largest packet sizes during hfp or during vsa/vpb/vfp
> +	 * should be computed according to byte lane, lane number and only
> +	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
> +	 */
> +	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> +		  | INVACT_LPCMD_TIME(4));
> +}
> +
> +static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
> +}
> +
> +static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> +					    struct drm_display_mode *mode)
> +{
> +	/*
> +	 * todo dw drv improvements
> +	 * only burst mode is supported here. For non-burst video modes,
> +	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
> +	 * DSI_VNPCR.NPSIZE... especially because this driver supports
> +	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> +	 */
> +	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
> +}
> +
> +static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * todo dw drv improvements
> +	 * compute high speed transmission counter timeout according
> +	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
> +	 */
> +	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> +	/*
> +	 * todo dw drv improvements
> +	 * the Bus-Turn-Around Timeout Counter should be computed
> +	 * according to byte lane...
> +	 */
> +	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> +	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> +}
> +
> +/* Get lane byte clock cycles. */
> +static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
> +					   struct drm_display_mode *mode,
> +					   u32 hcomponent)
> +{
> +	u32 frac, lbcc;
> +
> +	lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
> +
> +	frac = lbcc % mode->clock;
> +	lbcc = lbcc / mode->clock;
> +	if (frac)
> +		lbcc++;
> +
> +	return lbcc;
> +}
> +
> +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> +					  struct drm_display_mode *mode)
> +{
> +	u32 htotal, hsa, hbp, lbcc;
> +
> +	htotal = mode->htotal;
> +	hsa = mode->hsync_end - mode->hsync_start;
> +	hbp = mode->htotal - mode->hsync_end;
> +
> +	/*
> +	 * todo dw drv improvements
> +	 * computations below may be improved...
> +	 */
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> +	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> +	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> +
> +	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> +	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> +}
> +
> +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> +					       struct drm_display_mode *mode)
> +{
> +	u32 vactive, vsa, vfp, vbp;
> +
> +	vactive = mode->vdisplay;
> +	vsa = mode->vsync_end - mode->vsync_start;
> +	vfp = mode->vsync_start - mode->vdisplay;
> +	vbp = mode->vtotal - mode->vsync_end;
> +
> +	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> +	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> +	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> +	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> +}
> +
> +static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * todo dw drv improvements
> +	 * data & clock lane timers should be computed according to panel
> +	 * blankings and to the automatic clock lane control mode...
> +	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
> +	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> +	 */
> +	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
> +		  | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
> +
> +	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
> +		  | PHY_CLKLP2HS_TIME(0x40));
> +}
> +
> +static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> +{
> +	/*
> +	 * todo dw drv improvements
> +	 * stop wait time should be the maximum between host dsi
> +	 * and panel stop wait times
> +	 */
> +	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> +		  N_LANES(dsi->lanes));
> +}
> +
> +static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> +{
> +	dsi_read(dsi, DSI_INT_ST0);
> +	dsi_read(dsi, DSI_INT_ST1);
> +	dsi_write(dsi, DSI_INT_MSK0, 0);
> +	dsi_write(dsi, DSI_INT_MSK1, 0);
> +}
> +
> +static void dw_mipi_dsi_bridge_disable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +
> +	if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
> +		return;
> +
> +	if (clk_enable(dsi->pclk)) {
> +		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
> +		return;
> +	}
> +
> +	drm_panel_disable(dsi->panel);
> +
> +	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> +	drm_panel_unprepare(dsi->panel);
> +
> +	dw_mipi_dsi_disable(dsi);
> +	pm_runtime_put(dsi->dev);
> +	clk_disable(dsi->pclk);
> +	dsi->dpms_mode = DRM_MODE_DPMS_OFF;
> +}
> +
> +static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	struct drm_encoder *encoder = bridge->encoder;
> +	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
> +	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> +	void *priv_data = dsi->plat_data->priv_data;
> +	int ret;
> +
> +	if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
> +		return;
> +
> +	if (clk_enable(dsi->pclk)) {
> +		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
> +		return;
> +	}
> +
> +	ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->pllref_clk,
> +				     dsi->lanes, dsi->format, &dsi->lane_mbps);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
> +
> +	pm_runtime_get_sync(dsi->dev);
> +	dw_mipi_dsi_init(dsi);
> +	dw_mipi_dsi_dpi_config(dsi, mode);
> +	dw_mipi_dsi_packet_handler_config(dsi);
> +	dw_mipi_dsi_video_mode_config(dsi);
> +	dw_mipi_dsi_video_packet_config(dsi, mode);
> +	dw_mipi_dsi_command_mode_config(dsi);
> +	dw_mipi_dsi_line_timer_config(dsi, mode);
> +	dw_mipi_dsi_vertical_timing_config(dsi, mode);
> +	dw_mipi_dsi_dphy_timing_config(dsi);
> +	dw_mipi_dsi_dphy_interface_config(dsi);
> +	dw_mipi_dsi_clear_err(dsi);
> +
> +	/*
> +	 * todo dw drv improvements
> +	 * following command is inside dw_mipi_dsi_phy_init()

You mean in the dw_mipi_dsi_phy_init() implementation of the rockchip
driver?

The rockchip driver also calls:

	/* Start by clearing PHY state */
	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);

These registers also look like a part of the DW DSI block.

Also, the rockhip driver does something to configure grf_clks.
Can you mention a comment that they need to add a pdata quirk
here.

> +	 * but this function is also required here. We way move it in the
s/way/may
> +	 * phy but here we are using dsi regs...
> +	 * maybe add the waiting loop here too...
> +	 */
> +	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> +				     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> +
> +	ret = phy_ops->init(priv_data);
> +	if (ret)
> +		DRM_DEBUG_DRIVER("Phy init() failed\n");
> +
> +	dw_mipi_dsi_wait_for_two_frames(mode);
> +
> +	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> +	if (drm_panel_prepare(dsi->panel))
> +		dev_err(dsi->dev, "failed to prepare panel\n");
> +
> +	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
> +	drm_panel_enable(dsi->panel);
> +
> +	clk_disable(dsi->pclk);
> +
> +	dsi->dpms_mode = DRM_MODE_DPMS_ON;
> +}
> +
> +static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
> +{
> +	struct dw_mipi_dsi *dsi = con_to_dsi(connector);
> +
> +	return drm_panel_get_modes(dsi->panel);
> +}
> +
> +static enum drm_mode_status
> +dw_mipi_dsi_mode_valid(struct drm_connector *connector,
> +		       struct drm_display_mode *mode)
> +{
> +	struct dw_mipi_dsi *dsi = con_to_dsi(connector);
> +	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
> +	enum drm_mode_status mode_status = MODE_OK;
> +
> +	if (pdata->mode_valid)
> +		mode_status = pdata->mode_valid(pdata->priv_data,
> +						connector, mode);
> +
> +	return mode_status;
> +}
> +
> +static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
> +	.get_modes = dw_mipi_dsi_connector_get_modes,
> +	.mode_valid = dw_mipi_dsi_mode_valid,
> +};
> +
> +static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
> +{
> +	drm_connector_unregister(connector);
> +	drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
> +	.dpms = drm_atomic_helper_connector_dpms,
> +	.fill_modes = drm_helper_probe_single_connector_modes,
> +	.destroy = dw_mipi_dsi_drm_connector_destroy,
> +	.reset = drm_atomic_helper_connector_reset,
> +	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
> +{
> +	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
> +	struct drm_connector *connector = &dsi->connector;
> +
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found\n");
> +		return -ENODEV;
> +	}
> +
> +	/* Set the encoder type as caller does not know it */
> +	bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
> +
> +	connector->polled = DRM_CONNECTOR_POLL_HPD;
> +
> +	drm_connector_helper_add(connector,
> +				 &dw_mipi_dsi_connector_helper_funcs);
> +
> +	drm_connector_init(bridge->dev, connector,
> +			   &dw_mipi_dsi_atomic_connector_funcs,
> +			   DRM_MODE_CONNECTOR_DSI);
> +
> +	drm_mode_connector_attach_encoder(connector, bridge->encoder);
> +
> +	return 0;
> +}
> +
> +static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
> +	.enable = dw_mipi_dsi_bridge_enable,
> +	.disable = dw_mipi_dsi_bridge_disable,
> +	.attach = dw_mipi_dsi_bridge_attach,
> +};
> +
> +static struct dw_mipi_dsi *
> +__dw_mipi_dsi_probe(struct platform_device *pdev,
> +		    const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct reset_control *apb_rst;
> +	struct dw_mipi_dsi *dsi;
> +	struct resource *res;
> +	int ret;
> +
> +	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> +	if (!dsi)
> +		return ERR_PTR(-ENOMEM);
> +
> +	dsi->dev = dev;
> +	dsi->plat_data = plat_data;
> +	dsi->dpms_mode = DRM_MODE_DPMS_OFF;
> +
> +	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
> +		DRM_ERROR("Phy not properly configured\n");
> +		return ERR_PTR(-ENODEV);
> +	}
> +
> +	if (!plat_data->base) {
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +		if (!res)
> +			return ERR_PTR(-ENODEV);
> +
> +		dsi->base = devm_ioremap_resource(dev, res);
> +		if (IS_ERR(dsi->base))
> +			return ERR_PTR(-ENODEV);
> +
> +	} else {
> +		dsi->base = plat_data->base;
> +	}
> +
> +	dsi->pllref_clk = devm_clk_get(dev, "ref");

The hisil implementation doesn't seem to have a pllref_clk. Can you make
this either optional as you've done for apb_rst, or make it a part of pdata?

Thanks,
Archit

> +	if (IS_ERR(dsi->pllref_clk)) {
> +		ret = PTR_ERR(dsi->pllref_clk);
> +		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	dsi->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(dsi->pclk)) {
> +		ret = PTR_ERR(dsi->pclk);
> +		dev_err(dev, "Unable to get pclk: %d\n", ret);
> +		return ERR_PTR(ret);
> +	}
> +
> +	/*
> +	 * Note that the reset was not defined in the initial device tree, so
> +	 * we have to be prepared for it not being found.
> +	 */
> +	apb_rst = devm_reset_control_get(dev, "apb");
> +	if (IS_ERR(apb_rst)) {
> +		ret = PTR_ERR(apb_rst);
> +		if (ret == -ENOENT) {
> +			apb_rst = NULL;
> +		} else {
> +			dev_err(dev, "Unable to get reset control: %d\n", ret);
> +			return ERR_PTR(ret);
> +		}
> +	}
> +
> +	if (apb_rst) {
> +		ret = clk_prepare_enable(dsi->pclk);
> +		if (ret) {
> +			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
> +			return ERR_PTR(ret);
> +		}
> +
> +		reset_control_assert(apb_rst);
> +		usleep_range(10, 20);
> +		reset_control_deassert(apb_rst);
> +
> +		clk_disable(dsi->pclk);
> +	}
> +
> +	ret = clk_prepare_enable(dsi->pllref_clk);
> +	if (ret) {
> +		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
> +		return ERR_PTR(ret);
> +	}
> +
> +	pm_runtime_enable(dev);
> +
> +	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
> +	dsi->dsi_host.dev = dev;
> +	ret = mipi_dsi_host_register(&dsi->dsi_host);
> +	if (ret) {
> +		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
> +		goto err_cleanup;
> +	}
> +
> +	dsi->bridge.driver_private = dsi;
> +	dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
> +#ifdef CONFIG_OF
> +	dsi->bridge.of_node = pdev->dev.of_node;
> +#endif
> +
> +	clk_enable(dsi->pclk);
> +
> +	dev_set_drvdata(dev, dsi);
> +
> +	return dsi;
> +
> +err_cleanup:
> +	clk_disable_unprepare(dsi->pllref_clk);
> +
> +	return ERR_PTR(ret);
> +}
> +
> +static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
> +{
> +	pm_runtime_disable(dsi->dev);
> +	clk_disable_unprepare(dsi->pllref_clk);
> +}
> +
> +/*
> + * Probe/remove API, used from platforms based on the DRM bridge API.
> + */
> +int dw_mipi_dsi_probe(struct platform_device *pdev,
> +		      const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +	int ret;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	ret = drm_bridge_add(&dsi->bridge);
> +	if (ret < 0) {
> +		__dw_mipi_dsi_remove(dsi);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
> +
> +void dw_mipi_dsi_remove(struct platform_device *pdev)
> +{
> +	struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
> +
> +	mipi_dsi_host_unregister(&dsi->dsi_host);
> +	drm_bridge_remove(&dsi->bridge);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
> +
> +/*
> + * Bind/unbind API, used from platforms based on the component framework.
> + */
> +int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
> +		     const struct dw_mipi_dsi_plat_data *plat_data)
> +{
> +	struct dw_mipi_dsi *dsi;
> +	int ret;
> +
> +	dsi = __dw_mipi_dsi_probe(pdev, plat_data);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
> +	if (ret) {
> +		dw_mipi_dsi_remove(pdev);
> +		DRM_ERROR("Failed to initialize bridge with drm\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
> +
> +void dw_mipi_dsi_unbind(struct device *dev)
> +{
> +	struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
> +
> +	__dw_mipi_dsi_remove(dsi);
> +}
> +EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
> +
> +MODULE_AUTHOR("Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>");
> +MODULE_AUTHOR("Philippe Cornu <philippe.cornu-qxv4g6HH51o@public.gmane.org>");
> +MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:dw-mipi-dsi");
>

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