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Tue, 28 Apr 2026 05:15:49 -0500 Received: from [10.249.134.231] ([10.249.134.231]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 63SAFibP982649; Tue, 28 Apr 2026 05:15:45 -0500 Message-ID: <6aa8fd45-ec3d-4bd7-9b13-6c00e4fd4efc@ti.com> Date: Tue, 28 Apr 2026 15:45:43 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-j721s2-som-p0: add bootph-pre-ram property to pmic@4c To: "Thomas Richard (TI)" , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Thomas Petazzoni , , , , , , , References: <20260428-k3-j721s2-som-bootph-pre-ram-pmic-4c-v1-1-e8202ce955a0@bootlin.com> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <20260428-k3-j721s2-som-bootph-pre-ram-pmic-4c-v1-1-e8202ce955a0@bootlin.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001504:EE_|MW5PR10MB5737:EE_ X-MS-Office365-Filtering-Correlation-Id: ae707c20-c3c7-4194-8f27-08dea50f1fed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700016|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MnqscwMjyusMewP0XRc0XZnhVrm+oc5pxsAJ9KpIvoSRzfuKSFsAL287y2VZLOXQZVlzrgYg1/vJuw3nnWM+PQ9LllJCqpYmVgCcLDLuzuwtIV8a0p1I/ffqAB2+0nKu5WD6hMRzKR12/deBcQ5pcXxa3fILGV0St5w0IVyE5lBu0VQGM/T9dz5OVERV2jvyeBAHtPDO+c/MfbQto0bClTSe1JS11nCgA3BIDzij+k+lbpdWa/5OZYBGDvI9lebq4fowOb5yyjYtsXpxorviDadXotme5QhrWQZTQEXApVwS4KAgUgdsMgX/5hXQgMcSCQ+pnHUfvgLbJGW6PLojiwAglnjbFuh78nMfnCWx5o631v/mrgsRIM1QAFgufFWxKj6bBokG1DAxhro3Oj2eJKVmiFn3i5A4IRxseFuAFw1I3TsmnLqqXpG23OeWVMvD X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 10:15:51.1221 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae707c20-c3c7-4194-8f27-08dea50f1fed X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR10MB5737 On 4/28/2026 2:23 PM, Thomas Richard (TI) wrote: > On j721s2, pmic@4c is needed to exit the DDR from retention after pmic@4c to PMIC-A to align with schematic, please > suspend-to-ram. Add bootph-pre-ram property to make pmic@4c available to > the bootloader in the phase that sets up the DDR. > > Signed-off-by: Thomas Richard (TI) > --- > arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > index 12a38dd1514b..a19e535f4946 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > @@ -250,6 +250,7 @@ buckb1: buck1 { > regulator-max-microvolt = <1800000>; > regulator-always-on; > regulator-boot-on; > + bootph-pre-ram; > }; > > buckb2: buck2 { > > --- > base-commit: 59b04cb2325c07ddc1cc7d984bd8c8f89f161746 > change-id: 20260427-k3-j721s2-som-bootph-pre-ram-pmic-4c-744fb90b05a3 > > Best regards,