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[95.235.252.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a19ba624b3sm150533075e9.2.2026.10.12.05.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 05:02:22 -0700 (PDT) Message-ID: <6acccc4e.4c22a69b.132624.271f@mx.google.com> X-Google-Original-Message-ID: Date: Mon, 12 Oct 2026 14:02:19 +0200 From: Christian Marangi To: sashiko-reviews@lists.linux.dev Cc: lee@kernel.org, mfd@lists.linux.dev, conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org Subject: Re: [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch References: <20261009161102.38961-1-ansuelsmth@gmail.com> <20261009161102.38961-5-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sat, Oct 10, 2026 at 04:11:40PM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [Medium] mfd: overlapping regmap readable ranges for General Purpose and GPU timers > - [Low] mfd: structure and variable naming violates MFD API guidelines > -- > > commit 05d4dc95b969f0fcf66d11398aafad3e7eb7c7f1 > Author: Christian Marangi > > mfd: an8855: Add support for Airoha AN8855 Switch > > This commit adds support for the Airoha AN8855 Switch which provides > a DSA switch and a NVMEM provider. It utilizes the mdio-regmap driver > and registers a regmap for each internal PHY. > > > diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c > > new file mode 100644 > > index 0000000000000..a2778511dfefc > > --- /dev/null > > +++ b/drivers/mfd/airoha-an8855.c > [ ... ] > > +static const struct regmap_range an8855_readable_ranges[] = { > [ ... ] > > + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ > > + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ > > + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ > > [Severity: Medium] > Is this range definition correct? The General Purpose Timer range > (0x1000a100 to 0x1000a2ff) fully overlaps with the GPU timer range > (0x1000a200 to 0x1000a2ff). > > Could this be a typo in the hardware memory map definition? It seems like > the General Purpose Timer range might have been intended to end at > 0x1000a1ff to avoid overlapping and potential register access boundary > issues. > I have to double check this from documentation, but if possible I would like to fix this with a followup patch. > [ ... ] > > +static int an8855_core_probe(struct mdio_device *mdiodev) > > +{ > > + struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { }; > > + struct device *dev = &mdiodev->dev; > > + struct an8855_core *priv; > > + struct regmap *regmap; > > + int num_phys; > > + int i, ret; > > + > > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > > [Severity: Low] > This isn't a bug, but does this variable and structure naming align with MFD > subsystem conventions? > > The MFD guidelines suggest avoiding generic variable names like priv, and > instead recommend using ddata for the instance variable. Also, should the > struct name itself avoid hardcoding implementation details like core? > Naming it something closer to struct an8855 might better adhere to the > subsystem guidelines. > I already updated the struct, is it needed to also update the local variables? > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20261009161102.38961-1-ansuelsmth@gmail.com?part=4 -- Ansuel