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Fri, 19 Dec 2025 05:15:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFsxyK5lHLg3u33gOcm5o66CK8suco88/56FRjoiS6lVtwAhOZVk1W29HbjNE5Gu3ZcAxPv+w== X-Received: by 2002:a05:6a21:6d98:b0:364:86a:46b2 with SMTP id adf61e73a8af0-376a9ccbb0bmr3024453637.57.1766150142120; Fri, 19 Dec 2025 05:15:42 -0800 (PST) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e772ac06fsm2002400a91.11.2025.12.19.05.15.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Dec 2025 05:15:41 -0800 (PST) Message-ID: <6afcb26f-6f6a-41ef-ac45-976e5e2f17ae@oss.qualcomm.com> Date: Fri, 19 Dec 2025 18:45:32 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V8 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Jonathan Cameron Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org References: <20251127134036.209905-1-jishnu.prakash@oss.qualcomm.com> <20251127134036.209905-4-jishnu.prakash@oss.qualcomm.com> <20251207165349.72f80659@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20251207165349.72f80659@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=P6c3RyAu c=1 sm=1 tr=0 ts=69455000 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fLtpXVqzqxV2lCxwsoQA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: FN8G3tN0u1Zq_rATYvdfL0WCcws4fvlM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDExMCBTYWx0ZWRfX6OjNKZduE4T7 BP1Tq23R6HcqLXDrpvAyvS/aLVGHZRJm+c3ajkT7AABRnRz90Oiyy78KeUKG2rSP8HF1M1Nk+Zm UMWW2CvQFwHVWeqCNjEXLwKHAEtsu/vWkD+YbNJuZGRlD5BHCcu7tQVLF28TLMfktIM4zZZ63pE ia2oNeMXViUkJQ2rkaWw4GpHt0clmRxvyPxWB0JEparm9HNiIGY0DquTDFYt2jmeDFyFSUABP0r LM3bS1oP0SyvbSyQctbtckrAg4UBMsqu5mTp/YmEDXSy2UAcRdfRCOc0oypuEgb4z6ftS2/bh83 NcljMi1d2jWhn3AecKbpOr+A5e2F2gNQ+ffv0iss3IBByHmyc1gDgncVCzNNsXUTDzvllkSVRFW 42xDHzNRv2rtOJZxVqJiXxzX+D5VNAzAXU37mgO+FSZNQq2QbCff6y8B9QJ8+WOTyn9OUEJpXXX m0kzWZ9OxAqEJAh7PPQ== X-Proofpoint-GUID: FN8G3tN0u1Zq_rATYvdfL0WCcws4fvlM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_04,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190110 Hi Jonathan, On 12/7/2025 10:23 PM, Jonathan Cameron wrote: > On Thu, 27 Nov 2025 19:10:35 +0530 > Jishnu Prakash wrote: > >> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, >> with all SW communication to ADC going through PMK8550 which >> communicates with other PMICs through PBS. >> >> One major difference is that the register interface used here is that >> of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. >> There may be more than one SDAM used for ADC5 Gen3 and each has eight >> channels, which may be used for either immediate reads (same functionality >> as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements >> (same as ADC_TM functionality). >> >> By convention, we reserve the first channel of the first SDAM for all >> immediate reads and use the remaining channels across all SDAMs for >> ADC_TM monitoring functionality. >> >> Add support for PMIC5 Gen3 ADC driver for immediate read functionality. >> ADC_TM is implemented as an auxiliary thermal driver under this ADC >> driver. >> >> Signed-off-by: Jishnu Prakash > Hi Jishnu > > Biggest thing I noticed on a fresh review is that you include > very few headers. This only compiles (I think) because of lots > of deeply nested includes. General principle in kernel code is > to follow IWYU approach with a few exceptions. That makes code > much less prone to changes deep in the header hierarchy. > > You can even use the tooling that exists for clang to give you suggestions > though search around for config files (I posted one a long time back) > that reduce the noise somewhat. > > Jonathan > > >> diff --git a/drivers/iio/adc/qcom-adc5-gen3-common.c b/drivers/iio/adc/qcom-adc5-gen3-common.c >> new file mode 100644 >> index 000000000000..46bb09424f22 >> --- /dev/null >> +++ b/drivers/iio/adc/qcom-adc5-gen3-common.c >> @@ -0,0 +1,107 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> + * >> + * Code shared between the main and auxiliary Qualcomm PMIC voltage ADCs >> + * of type ADC5 Gen3. >> + */ >> + >> +#include >> +#include >> +#include >> +#include > This seems like very light set of includes. > If nothing else should be seeing linux/types.h I think > > In general try to follow include what you use principles (loosely as some > conventions exit for not including particular headers). > I have a question about this - I'm including some header files in my newly added common header file too (include/linux/iio/adc/qcom-adc5-gen3-common.h). Do I need to repeat those in the driver files where this header is already included? > Sorry I didn't notice this in earlier reviews! > > >> diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c >> new file mode 100644 >> index 000000000000..effd4bd49989 >> --- /dev/null >> +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c > >> +/** >> + * struct adc5_chip - ADC private structure. >> + * @dev: SPMI ADC5 Gen3 device. >> + * @dev_data: Top-level ADC device data. >> + * @nchannels: number of ADC channels. >> + * @chan_props: array of ADC channel properties. >> + * @iio_chans: array of IIO channels specification. >> + * @complete: ADC result notification after interrupt is received. >> + * @lock: ADC lock for access to the peripheral, to prevent concurrent >> + * requests from multiple clients. >> + * @data: software configuration data. >> + * @n_tm_channels: number of ADC channels used for TM measurements. >> + * @tm_aux: pointer to auxiliary TM device. >> + */ >> +struct adc5_chip { >> + struct device *dev; >> + struct adc5_device_data dev_data; >> + unsigned int nchannels; >> + struct adc5_channel_prop *chan_props; >> + struct iio_chan_spec *iio_chans; >> + struct completion complete; >> + /* >> + * lock for access to the peripheral, to prevent concurrent requests >> + * from multiple clients. >> + */ > > Whilst checkpatch is dumb on this and complains if you don't have a comment > here feel free to drop it as the one in the kernel-doc is enough. > I'll make this change in the next patch series. Thanks, Jishnu >> + struct mutex lock; >> + const struct adc5_data *data; >> + unsigned int n_tm_channels; >> + struct auxiliary_device *tm_aux; >> +}; > > >>