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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43d82dedd6fsm163362265e9.7.2025.03.31.01.38.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Mar 2025 01:38:18 -0700 (PDT) Message-ID: <6bca05ac-13d0-4197-b4af-5509884c83c6@linaro.org> Date: Mon, 31 Mar 2025 10:38:17 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: timer: Add NXP System Timer Module To: Krzysztof Kozlowski , tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, thomas.fossati@linaro.org, Larisa.Grigore@nxp.com, ghennadi.procopciuc@nxp.com, S32@nxp.com, Ghennadi Procopciuc , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/STM32 ARCHITECTURE" , "moderated list:ARM/STM32 ARCHITECTURE" References: <20250328134208.2183653-1-daniel.lezcano@linaro.org> <20250328134208.2183653-2-daniel.lezcano@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 29/03/2025 06:03, Krzysztof Kozlowski wrote: > On 28/03/2025 14:42, Daniel Lezcano wrote: >> Add the System Timer Module description found on the NXP s32 platform >> and the compatible for the s32g2 variant. >> >> Cc: Ghennadi Procopciuc >> Cc: Krzysztof Kozlowski >> Cc: Thomas Fossati >> Signed-off-by: Daniel Lezcano >> --- > > I got only this patch, no cover letter, no changelog. What happened here? My bad, my scripts needs some more work :) Will Cc you in the next version >> .../bindings/timer/nxp,stm-timer.yaml | 50 +++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/nxp,stm-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/nxp,stm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,stm-timer.yaml >> new file mode 100644 >> index 000000000000..a9c0151d62be >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/nxp,stm-timer.yaml > > Filename following compatible. > >> @@ -0,0 +1,50 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/timer/nxp,stm-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: NXP System Timer Module (STM) >> + >> +maintainers: >> + - Daniel Lezcano >> + >> +description: >> + The System Timer Module supports commonly required system and application >> + software timing functions. STM includes a 32-bit count-up timer and four >> + 32-bit compare channels with a separate interrupt source for each channel. >> + The timer is driven by the STM module clock divided by an 8-bit prescale >> + value. >> + >> +properties: >> + compatible: >> + enum: >> + - nxp,s32g-stm > > Previously it was told to me there is no such soc as s32g but they are > named differently, e.g. s32g2. See other bindings. > > Please consult internally and come with one unified approach to all NXP > bindings. Otherwise, if this is a real soc, fix this for top level > compatibles, because there is no s32g there either. > > This applies to all NXP-related patches (which I am sure was previously > discussed on the lists). > > What is confusing: previous compatible was correct and I did not ask to > change it. Yeah, I think the answer is straightforward. It is s32g2 and s32g3, the two platforms having the STM. I'll will fix the compatibles. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog