* [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only)
@ 2023-02-01 1:00 Richard Acayan
2023-02-01 1:00 ` [PATCH v4 1/2] arm64: dts: qcom: sdm670: add interconnects Richard Acayan
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Richard Acayan @ 2023-02-01 1:00 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree
Cc: Odelu Kukatla, Luca Weiss, Richard Acayan
Changes since v4 (20230111005155.50452-1-mailingradian@gmail.com):
- drop applied bindings and driver patches (previously 1-2/4)
Changes since v3:
- fix a merge conflict on linux-next (1/4)
Changes since v2:
- change qcom,sdm670.h to qcom,sdm670-rpmh.h (2/4)
- use SPDX v3 license identifiers (1/4, 2/4)
- accumulate ack tag (1/4)
- format changelog (0/4)
Changes since v1:
- change qcom,sdm670.h to qcom,sdm670-rpmh.h (1/4, 4/4)
This series adds interconnects nodes and consumers to the Snapdragon 670.
Richard Acayan (2):
arm64: dts: qcom: sdm670: add interconnects
arm64: dts: qcom: sdm670: add opps for peripherals
arch/arm64/boot/dts/qcom/sdm670.dtsi | 165 +++++++++++++++++++++++++++
1 file changed, 165 insertions(+)
--
2.39.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v4 1/2] arm64: dts: qcom: sdm670: add interconnects 2023-02-01 1:00 [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Richard Acayan @ 2023-02-01 1:00 ` Richard Acayan 2023-02-01 1:00 ` [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals Richard Acayan ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Richard Acayan @ 2023-02-01 1:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree Cc: Odelu Kukatla, Luca Weiss, Richard Acayan The interconnects for Snapdragon 670 can be controlled. Add their corresponding nodes in the device tree. Signed-off-by: Richard Acayan <mailingradian@gmail.com> --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index ec9946e5f08d..02f14692dd9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -788,6 +788,55 @@ i2c15: i2c@a9c000 { }; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm670-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm670-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm670-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm670-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm670-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm670-aggre2-noc"; + reg = <0 0x01700000 0 0x1f300>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm670-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm670-tlmm"; reg = <0 0x03400000 0 0xc00000>; @@ -1083,6 +1132,13 @@ apps_smmu: iommu@15000000 { <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm670-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x179c0000 0 0x10000>, -- 2.39.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals 2023-02-01 1:00 [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Richard Acayan 2023-02-01 1:00 ` [PATCH v4 1/2] arm64: dts: qcom: sdm670: add interconnects Richard Acayan @ 2023-02-01 1:00 ` Richard Acayan 2023-02-01 18:51 ` Konrad Dybcio 2023-02-09 4:23 ` [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Bjorn Andersson 2023-03-15 23:35 ` (subset) " Bjorn Andersson 3 siblings, 1 reply; 6+ messages in thread From: Richard Acayan @ 2023-02-01 1:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree Cc: Odelu Kukatla, Luca Weiss, Richard Acayan The interconnects are now in place. Add Operating Performance Points for them to allow the kernel to properly manage them. Signed-off-by: Richard Acayan <mailingradian@gmail.com> --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 02f14692dd9d..c5f839dd1c6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -430,6 +431,10 @@ sdhc_1: mmc@7c4000 { <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; clock-names = "iface", "core", "xo", "ice", "bus"; + interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; iommus = <&apps_smmu 0x140 0xf>; @@ -442,6 +447,38 @@ sdhc_1: mmc@7c4000 { non-removable; status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_min_svs>; + opp-peak-kBps = <80000 80000>; + opp-avg-kBps = <52286 80000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <200000 100000>; + opp-avg-kBps = <130718 100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <200000 130000>; + opp-avg-kBps = <130718 130000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <4096000 4096000>; + opp-avg-kBps = <1338562 1338562>; + }; + }; }; gpi_dma0: dma-controller@800000 { @@ -477,6 +514,8 @@ qupv3_id_0: geniqup@8c0000 { #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -490,6 +529,10 @@ i2c0: i2c@880000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -507,6 +550,10 @@ i2c1: i2c@884000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -524,6 +571,10 @@ i2c2: i2c@888000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -541,6 +592,10 @@ i2c3: i2c@88c000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -558,6 +613,10 @@ i2c4: i2c@890000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -575,6 +634,10 @@ i2c5: i2c@894000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -592,6 +655,10 @@ i2c6: i2c@898000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -609,6 +676,10 @@ i2c7: i2c@89c000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -649,6 +720,8 @@ qupv3_id_1: geniqup@ac0000 { #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -662,6 +735,10 @@ i2c8: i2c@a80000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -679,6 +756,10 @@ i2c9: i2c@a84000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -696,6 +777,10 @@ i2c10: i2c@a88000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -713,6 +798,10 @@ i2c11: i2c@a8c000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -730,6 +819,10 @@ i2c12: i2c@a90000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -747,6 +840,10 @@ i2c13: i2c@a94000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -764,6 +861,10 @@ i2c14: i2c@a98000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -781,6 +882,10 @@ i2c15: i2c@a9c000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1028,6 +1133,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + status = "disabled"; usb_1_dwc3: usb@a600000 { -- 2.39.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals 2023-02-01 1:00 ` [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals Richard Acayan @ 2023-02-01 18:51 ` Konrad Dybcio 0 siblings, 0 replies; 6+ messages in thread From: Konrad Dybcio @ 2023-02-01 18:51 UTC (permalink / raw) To: Richard Acayan, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree Cc: Odelu Kukatla, Luca Weiss On 1.02.2023 02:00, Richard Acayan wrote: > The interconnects are now in place. Add Operating Performance Points for > them to allow the kernel to properly manage them. You're really mostly adding interconnect paths in this patch. > > Signed-off-by: Richard Acayan <mailingradian@gmail.com> > --- For the contents though: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sdm670.dtsi | 109 +++++++++++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi > index 02f14692dd9d..c5f839dd1c6e 100644 > --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi > @@ -10,6 +10,7 @@ > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/phy/phy-qcom-qusb2.h> > #include <dt-bindings/power/qcom-rpmpd.h> > @@ -430,6 +431,10 @@ sdhc_1: mmc@7c4000 { > <&gcc GCC_SDCC1_ICE_CORE_CLK>, > <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; > clock-names = "iface", "core", "xo", "ice", "bus"; > + interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; > + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > + operating-points-v2 = <&sdhc1_opp_table>; > > iommus = <&apps_smmu 0x140 0xf>; > > @@ -442,6 +447,38 @@ sdhc_1: mmc@7c4000 { > non-removable; > > status = "disabled"; > + > + sdhc1_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-20000000 { > + opp-hz = /bits/ 64 <20000000>; > + required-opps = <&rpmhpd_opp_min_svs>; > + opp-peak-kBps = <80000 80000>; > + opp-avg-kBps = <52286 80000>; > + }; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + opp-peak-kBps = <200000 100000>; > + opp-avg-kBps = <130718 100000>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <200000 130000>; > + opp-avg-kBps = <130718 130000>; > + }; > + > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <4096000 4096000>; > + opp-avg-kBps = <1338562 1338562>; > + }; > + }; > }; > > gpi_dma0: dma-controller@800000 { > @@ -477,6 +514,8 @@ qupv3_id_0: geniqup@8c0000 { > #address-cells = <2>; > #size-cells = <2>; > ranges; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; > + interconnect-names = "qup-core"; > status = "disabled"; > > i2c0: i2c@880000 { > @@ -490,6 +529,10 @@ i2c0: i2c@880000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, > <&gpi_dma0 1 0 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -507,6 +550,10 @@ i2c1: i2c@884000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, > <&gpi_dma0 1 1 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -524,6 +571,10 @@ i2c2: i2c@888000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, > <&gpi_dma0 1 2 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -541,6 +592,10 @@ i2c3: i2c@88c000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, > <&gpi_dma0 1 3 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -558,6 +613,10 @@ i2c4: i2c@890000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, > <&gpi_dma0 1 4 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -575,6 +634,10 @@ i2c5: i2c@894000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, > <&gpi_dma0 1 5 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -592,6 +655,10 @@ i2c6: i2c@898000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, > <&gpi_dma0 1 6 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -609,6 +676,10 @@ i2c7: i2c@89c000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, > + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, > <&gpi_dma0 1 7 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -649,6 +720,8 @@ qupv3_id_1: geniqup@ac0000 { > #address-cells = <2>; > #size-cells = <2>; > ranges; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; > + interconnect-names = "qup-core"; > status = "disabled"; > > i2c8: i2c@a80000 { > @@ -662,6 +735,10 @@ i2c8: i2c@a80000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, > <&gpi_dma1 1 0 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -679,6 +756,10 @@ i2c9: i2c@a84000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, > <&gpi_dma1 1 1 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -696,6 +777,10 @@ i2c10: i2c@a88000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, > <&gpi_dma1 1 2 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -713,6 +798,10 @@ i2c11: i2c@a8c000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, > <&gpi_dma1 1 3 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -730,6 +819,10 @@ i2c12: i2c@a90000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, > <&gpi_dma1 1 4 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -747,6 +840,10 @@ i2c13: i2c@a94000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, > <&gpi_dma1 1 5 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -764,6 +861,10 @@ i2c14: i2c@a98000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, > <&gpi_dma1 1 6 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -781,6 +882,10 @@ i2c15: i2c@a9c000 { > #address-cells = <1>; > #size-cells = <0>; > power-domains = <&rpmhpd SDM670_CX>; > + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, > + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, > <&gpi_dma1 1 7 QCOM_GPI_I2C>; > dma-names = "tx", "rx"; > @@ -1028,6 +1133,10 @@ usb_1: usb@a6f8800 { > > resets = <&gcc GCC_USB30_PRIM_BCR>; > > + interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, > + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > status = "disabled"; > > usb_1_dwc3: usb@a600000 { ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) 2023-02-01 1:00 [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Richard Acayan 2023-02-01 1:00 ` [PATCH v4 1/2] arm64: dts: qcom: sdm670: add interconnects Richard Acayan 2023-02-01 1:00 ` [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals Richard Acayan @ 2023-02-09 4:23 ` Bjorn Andersson 2023-03-15 23:35 ` (subset) " Bjorn Andersson 3 siblings, 0 replies; 6+ messages in thread From: Bjorn Andersson @ 2023-02-09 4:23 UTC (permalink / raw) To: Andy Gross, Rob Herring, Konrad Dybcio, devicetree, Richard Acayan, Krzysztof Kozlowski, linux-arm-msm Cc: Odelu Kukatla, Luca Weiss On Tue, 31 Jan 2023 20:00:18 -0500, Richard Acayan wrote: > Changes since v4 (20230111005155.50452-1-mailingradian@gmail.com): > - drop applied bindings and driver patches (previously 1-2/4) > > Changes since v3: > - fix a merge conflict on linux-next (1/4) > > Changes since v2: > - change qcom,sdm670.h to qcom,sdm670-rpmh.h (2/4) > - use SPDX v3 license identifiers (1/4, 2/4) > - accumulate ack tag (1/4) > - format changelog (0/4) > > [...] Applied, thanks! [1/2] arm64: dts: qcom: sdm670: add interconnects commit: 0daef104e4b1d945ac81cb10e35c29f82695b10a [2/2] arm64: dts: qcom: sdm670: add opps for peripherals (no commit info) Best regards, -- Bjorn Andersson <andersson@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: (subset) [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) 2023-02-01 1:00 [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Richard Acayan ` (2 preceding siblings ...) 2023-02-09 4:23 ` [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Bjorn Andersson @ 2023-03-15 23:35 ` Bjorn Andersson 3 siblings, 0 replies; 6+ messages in thread From: Bjorn Andersson @ 2023-03-15 23:35 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, Konrad Dybcio, devicetree, Richard Acayan, Andy Gross Cc: Odelu Kukatla, Luca Weiss On Tue, 31 Jan 2023 20:00:18 -0500, Richard Acayan wrote: > Changes since v4 (20230111005155.50452-1-mailingradian@gmail.com): > - drop applied bindings and driver patches (previously 1-2/4) > > Changes since v3: > - fix a merge conflict on linux-next (1/4) > > Changes since v2: > - change qcom,sdm670.h to qcom,sdm670-rpmh.h (2/4) > - use SPDX v3 license identifiers (1/4, 2/4) > - accumulate ack tag (1/4) > - format changelog (0/4) > > [...] Applied, thanks! [2/2] arm64: dts: qcom: sdm670: add opps for peripherals commit: 17289c0165bdb61a585e8e937b80defc376dbfde Best regards, -- Bjorn Andersson <andersson@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-03-15 23:49 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-02-01 1:00 [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Richard Acayan 2023-02-01 1:00 ` [PATCH v4 1/2] arm64: dts: qcom: sdm670: add interconnects Richard Acayan 2023-02-01 1:00 ` [PATCH v4 2/2] arm64: dts: qcom: sdm670: add opps for peripherals Richard Acayan 2023-02-01 18:51 ` Konrad Dybcio 2023-02-09 4:23 ` [PATCH v4 0/2] SDM670 Interconnects (now with dts patches only) Bjorn Andersson 2023-03-15 23:35 ` (subset) " Bjorn Andersson
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