From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout-p-103.mailbox.org (mout-p-103.mailbox.org [80.241.56.161]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CFD6364943; Thu, 9 Jul 2026 15:23:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.161 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783610611; cv=none; b=HHwLFyW4ULMbzme28gMQMtd9c2OAEOlv6CNKx/hRx+SMyAij9SYzv7BHlhwkeioz4aTrLikhcT9QkWZ3DLklZ41Vh1ItveNGyNLBtctf92W6UEP7qhtC7Pif3JW/lS/5aHJ4/C4g1GeOSf6b/aTLEj3Icr7E2cSrUTEg3XlU0yk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783610611; c=relaxed/simple; bh=FGj4BXdhDBDAGB4iwVbKiirOotKTnPLYsioMLbfUeUA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Q3juqexYkXskWGmCDZeGO5bvn9GCPcAocBjM8QSqp31FI1FoOH3RWISKY8Dvzaw2kbWWc46CaHBNUPP9Z94sk+5fXoBLfpeXuuMpHLCPa4wcs6gUlZus/XBmo1YqGYQ0JesUv9ZLwEayRmw3muZnrEImjAlyvIEQm+mOyMMuXXE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=BQ7qj2ik; arc=none smtp.client-ip=80.241.56.161 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="BQ7qj2ik" Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA512) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 4gwzHx3V6xzKnRd; Thu, 09 Jul 2026 17:23:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1783610605; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3DJtdglWdhtyGucyQVZjA4gR9eVcUWIO30Bf0LYMArA=; b=BQ7qj2ikuao6hCeNkVjToIpnnOPPxG5jLL+0iwcDY8+7B7zpJJg/zpTeSP5IbLZ8+ZWSRw 6d2K7pJtenD3l95c1cNZ607GCFfxVCL0xxYrQ4HPV6X67laguX9IYzI47FAe+b26xXYuyf IbB8N0JFDswID8N6f56VF8LqEBBu647mV4rLfIgEecghLbjO76iBIWz5NEyCaDXcxDx1GG /O1Ee4jE3Xd5C06TR67+43tHw3bMAZ5jcrb+UdDsi0yjhGF6mm9KwxUhpF8YLHx8yyDfwN b3Dr6ijdLOJDKKBhZvUuNkfh4kVcJPO+PxgQAQm7HO8qhwYCGZCUcuGspnEq3A== Message-ID: <6c93677c-974b-46d5-aa81-1ab04c8dd940@mailbox.org> Date: Thu, 9 Jul 2026 17:23:21 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: (subset) [PATCH v4 0/5] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS To: Manivannan Sadhasivam , linux-pci@vger.kernel.org Cc: =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Catalin Marinas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Marc Zyngier , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <20260707203743.88299-1-marek.vasut+renesas@mailbox.org> <178360186732.755595.3582150626313807959.b4-ty@b4> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: 4a5df62b25b95807fda X-MBO-RS-META: t18uwoiuq7fkdmahe51a9qkz95ma4n46 On 7/9/26 2:59 PM, Manivannan Sadhasivam wrote: > On Thu, Jul 09, 2026 at 02:57:47PM +0200, Manivannan Sadhasivam wrote: >> >> On Tue, 07 Jul 2026 22:35:38 +0200, Marek Vasut wrote: >>> Configure all R-Car Gen4 PCIe controller MSI registers fully, both in >>> case MSI are enabled and disabled. >>> >>> Patch GIC ITS driver and add quirks for R-Car Gen4 GIC ITS, which is >>> configured to 32-bit address width for AXI or APB interface. >>> >>> Switch R-Car V4H to use GIC ITS in its DT and describe the GIC ITS >>> implementation cacheable and shareable limitations. >>> >>> [...] >> >> Applied, thanks! >> >> [3/5] irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling >> commit: 96b193897fd374fcb63a782c52f8b079134d0222 >> [4/5] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround >> commit: 14e8394423ffd4fd28884ec8b4d5ba15be6e7e0d > > B4 got confused here. I applied all 4 patches. Understood. 5/5 should go through Geert / Renesas SoC tree ? Thank you !