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([2a02:810d:15c0:828:ff33:9b14:bdd2:a3da]) by smtp.gmail.com with ESMTPSA id d27-20020a50f69b000000b004acb696a0f6sm8592200edn.91.2023.03.08.11.17.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Mar 2023 11:17:33 -0800 (PST) Message-ID: <6cbe6c71-2d2d-0f79-1270-7f8ed2ddc1d6@linaro.org> Date: Wed, 8 Mar 2023 20:17:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings Content-Language: en-US To: Biju Das , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Geert Uytterhoeven , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , Fabrizio Castro References: <20230220131307.269100-1-biju.das.jz@bp.renesas.com> <20230220131307.269100-2-biju.das.jz@bp.renesas.com> <36e06397-2189-4f1b-99cc-d39e720ebc71@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/03/2023 19:55, Biju Das wrote: > > Renesas 8T49N241 has 4 outputs, 1 integral and 3 fractional dividers. > The 8T49N241 accepts up to two differential or single-ended input clocks > and a fundamental-mode crystal input. The internal PLL can lock to either > of the input reference clocks or to the crystal to behave as a frequency > synthesizer. > > Signed-off-by: Alex Helms > Reviewed-by: Rob Herring Ah, indeed, fine then. >> >>>> >>>>> + >>>>> + renesas,clock-flags: >>>>> + description: Flags used in common clock frame work for configuring >>>>> + clk outputs. See include/linux/clk-provider.h >>>> >>>> These are not bindings, so why do you non-bindings constants as bindings? >>>> They can change anytime. Choose one: >>>> 1. Drop entire property, >>>> 2. Make it a proper binding property, so an ABI and explain why this >>>> is DT specific. None of clock providers have to do it, so you need >>>> here good explanation. >>> >>> I will choose 2 and will explain as user should be allowed to >>> configure the output clock from clk generator, so that it has >>> flexibility for >>> 1) changing the rates (propagate rate change up one level) >>> 2) fixed always >>> 3) don't gate the ouput clk at all. >> >> User's choice is task for user-space, so not a good explanation for DT. > > I don't think clock generator HW has any business with user space. > > It is clk generator HW specific. Clk generator is vital component which > provides clocks to the system. Every clock controller is vital... > We are providing some hardware feature which > is exposed as dt properties. > > Like clock output is fixed rate clock or dynamic rate clock/ OK, I wait then for proper description which will explain and justify this. Best regards, Krzysztof