From: Matthias Brugger <matthias.bgg@gmail.com>
To: "Nancy.Lin" <nancy.lin@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
wim@linux-watchdog.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux@roeck-us.net
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, llvm@lists.linux.dev,
singo.chang@mediatek.com, srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v17 07/21] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
Date: Fri, 22 Apr 2022 13:37:17 +0200 [thread overview]
Message-ID: <6e06f2a0-ee9b-4cf4-85a3-243ed3121c50@gmail.com> (raw)
In-Reply-To: <20220416020749.29010-8-nancy.lin@mediatek.com>
On 16/04/2022 04:07, Nancy.Lin wrote:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++-----------
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 27 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 5469073e3073..0a286fa5a824 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -139,6 +139,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> #define MT8195_VDO1_HDR_TOP_CFG 0xd00
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index ea04aa2c3840..d7c806f9e494 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -20,6 +20,8 @@
> #include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .routes = mmsys_mt8186_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> @@ -148,6 +153,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .clk_driver = "clk-mt8195-vdo1",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
> + .num_resets = 64,
> };
>
> static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> @@ -234,18 +241,22 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
> {
> struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> unsigned long flags;
> + u32 offset;
> u32 reg;
>
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = id % MMSYS_SW_RESET_PER_REG;
> +
> spin_lock_irqsave(&mmsys->lock, flags);
>
> - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset + offset);
>
> if (assert)
> reg &= ~BIT(id);
> else
> reg |= BIT(id);
>
> - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset + offset);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> @@ -360,18 +371,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - spin_lock_init(&mmsys->lock);
> -
> - mmsys->rcdev.owner = THIS_MODULE;
> - mmsys->rcdev.nr_resets = 32;
> - mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> - mmsys->rcdev.of_node = pdev->dev.of_node;
> - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> - if (ret) {
> - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> - return ret;
> - }
> -
I'm not sure why you move that code block. It's not explained in the commit message.
Regards,
Matthias
next parent reply other threads:[~2022-04-22 11:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220416020749.29010-1-nancy.lin@mediatek.com>
[not found] ` <20220416020749.29010-8-nancy.lin@mediatek.com>
2022-04-22 11:37 ` Matthias Brugger [this message]
[not found] ` <20220416020749.29010-7-nancy.lin@mediatek.com>
2022-04-22 11:37 ` [PATCH v17 06/21] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 Matthias Brugger
[not found] ` <20220416020749.29010-12-nancy.lin@mediatek.com>
2022-04-22 11:48 ` [PATCH v17 11/21] drm/mediatek: add display merge start/stop API for cmdq support Matthias Brugger
2022-04-25 13:32 ` Chun-Kuang Hu
2022-04-25 15:27 ` Matthias Brugger
[not found] ` <20220416020749.29010-4-nancy.lin@mediatek.com>
2022-04-25 9:54 ` [PATCH v17 03/21] dt-bindings: mediatek: add ethdr definition for mt8195 Philipp Zabel
[not found] ` <20220416020749.29010-14-nancy.lin@mediatek.com>
2022-04-25 9:58 ` [PATCH v17 13/21] drm/mediatek: add display merge async reset control Philipp Zabel
[not found] ` <20220416020749.29010-15-nancy.lin@mediatek.com>
2022-04-25 10:00 ` [PATCH v17 14/21] drm/mediatek: add ETHDR support for MT8195 Philipp Zabel
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