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Mon, 1 Sep 2025 03:05:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CE.mail.protection.outlook.com (10.167.240.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9094.14 via Frontend Transport; Mon, 1 Sep 2025 03:04:59 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 979AC41604E2; Mon, 1 Sep 2025 11:04:58 +0800 (CST) Message-ID: <6e195d6e-2d3f-4550-bee1-05e085832034@cixtech.com> Date: Mon, 1 Sep 2025 11:04:58 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 12/15] PCI: sky1: Add PCIe host support for CIX Sky1 To: Manivannan Sadhasivam Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250819115239.4170604-1-hans.zhang@cixtech.com> <20250819115239.4170604-13-hans.zhang@cixtech.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 03:04:59.5067 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbd0aaa3-dcb6-478d-40c9-08dde9045680 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CE.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR0601MB5568 On 2025/8/30 21:29, Manivannan Sadhasivam wrote: > [Some people who received this message don't often get email from mani@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL > > On Tue, Aug 19, 2025 at 07:52:36PM GMT, hans.zhang@cixtech.com wrote: >> From: Hans Zhang >> >> Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based >> on the Cadence PCIe core. >> >> Supports MSI/MSI-x via GICv3, Single Virtual Channel, Single Function. >> >> Signed-off-by: Hans Zhang >> --- >> Changes for v8: >> - Optimization of CIX SKY1 Root Port driver. (Bjorn and Krzysztof) >> - Use devm_platform_ioremap_resource_byname. >> --- >> drivers/pci/controller/cadence/Kconfig | 15 ++ >> drivers/pci/controller/cadence/Makefile | 1 + >> drivers/pci/controller/cadence/pci-sky1.c | 232 ++++++++++++++++++++++ >> 3 files changed, 248 insertions(+) >> create mode 100644 drivers/pci/controller/cadence/pci-sky1.c >> >> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig >> index 117677a23d68..26a248cdc78a 100644 >> --- a/drivers/pci/controller/cadence/Kconfig >> +++ b/drivers/pci/controller/cadence/Kconfig >> @@ -42,6 +42,21 @@ config PCIE_CADENCE_PLAT_EP >> endpoint mode. This PCIe controller may be embedded into many >> different vendors SoCs. >> >> +config PCI_SKY1_HOST >> + tristate "CIX SKY1 PCIe controller (host mode)" >> + depends on OF >> + select PCIE_CADENCE_HOST >> + select PCI_ECAM >> + help >> + Say Y here if you want to support the CIX SKY1 PCIe platform >> + controller in host mode. CIX SKY1 PCIe controller uses Cadence >> + HPA (High Performance Architecture IP [Second generation of >> + Cadence PCIe IP]) >> + >> + This driver requires Cadence PCIe core infrastructure >> + (PCIE_CADENCE_HOST) and hardware platform adaptation layer >> + to function. >> + >> config PCI_J721E >> tristate >> select PCIE_CADENCE_HOST if PCI_J721E_HOST != n >> diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile >> index de4ddae7aca4..40d7c6e98b4d 100644 >> --- a/drivers/pci/controller/cadence/Makefile >> +++ b/drivers/pci/controller/cadence/Makefile >> @@ -8,3 +8,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o >> obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o >> obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o >> obj-$(CONFIG_PCI_J721E) += pci-j721e.o >> +obj-$(CONFIG_PCI_SKY1_HOST) += pci-sky1.o >> diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c >> new file mode 100644 >> index 000000000000..7dd3546275c5 >> --- /dev/null >> +++ b/drivers/pci/controller/cadence/pci-sky1.c >> @@ -0,0 +1,232 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe controller driver for CIX's sky1 SoCs >> + * > > No copyright for CIX tech? Dear Mani, Thank you very much for your reply. Will add. > >> + * Author: Hans Zhang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-cadence.h" >> +#include "pcie-cadence-host-common.h" >> + >> +#define STRAP_REG(n) ((n) * 0x04) >> +#define STATUS_REG(n) ((n) * 0x04) >> +#define LINK_TRAINING_ENABLE BIT(0) >> +#define LINK_COMPLETE BIT(0) > > Extra space. Will change. > >> + >> +#define SKY1_IP_REG_BANK 0x1000 >> +#define SKY1_IP_CFG_CTRL_REG_BANK 0x4c00 >> +#define SKY1_IP_AXI_MASTER_COMMON 0xf000 >> +#define SKY1_AXI_SLAVE 0x9000 >> +#define SKY1_AXI_MASTER 0xb000 >> +#define SKY1_AXI_HLS_REGISTERS 0xc000 >> +#define SKY1_AXI_RAS_REGISTERS 0xe000 >> +#define SKY1_DTI_REGISTERS 0xd000 >> + >> +#define IP_REG_I_DBG_STS_0 0x420 >> + >> +struct sky1_pcie { >> + struct cdns_pcie *cdns_pcie; >> + struct cdns_pcie_rc *cdns_pcie_rc; >> + >> + struct resource *cfg_res; >> + struct resource *msg_res; >> + struct pci_config_window *cfg; >> + void __iomem *strap_base; >> + void __iomem *status_base; >> + void __iomem *reg_base; >> + void __iomem *cfg_base; >> + void __iomem *msg_base; >> +}; >> + >> +static int sky1_pcie_resource_get(struct platform_device *pdev, >> + struct sky1_pcie *pcie) >> +{ >> + struct device *dev = &pdev->dev; >> + struct resource *res; >> + void __iomem *base; >> + >> + base = devm_platform_ioremap_resource_byname(pdev, "reg"); >> + if (IS_ERR(base)) >> + return dev_err_probe(dev, PTR_ERR(base), >> + "unable to find reg registers\n"); > > "unable to find \"reg\" registers". Same for below prints. Will change. > >> + pcie->reg_base = base; >> + >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); >> + if (!res) >> + return dev_err_probe(dev, ENXIO, "unable to get cfg resource\n"); >> + pcie->cfg_res = res; >> + >> + base = devm_platform_ioremap_resource_byname(pdev, "rcsu_strap"); >> + if (IS_ERR(base)) >> + return dev_err_probe(dev, PTR_ERR(base), >> + "unable to find rcsu strap registers\n"); >> + pcie->strap_base = base; >> + >> + base = devm_platform_ioremap_resource_byname(pdev, "rcsu_status"); >> + if (IS_ERR(base)) >> + return dev_err_probe(dev, PTR_ERR(base), >> + "unable to find rcsu status registers\n"); >> + pcie->status_base = base; >> + >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); >> + if (!res) >> + return dev_err_probe(dev, ENXIO, "unable to get msg resource\n"); >> + pcie->msg_res = res; >> + pcie->msg_base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(pcie->msg_base)) { >> + return dev_err_probe(dev, PTR_ERR(pcie->msg_base), >> + "unable to ioremap msg resource\n"); >> + } >> + >> + return 0; >> +} >> + >> +static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie) >> +{ >> + struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); >> + u32 val; >> + >> + val = readl(pcie->strap_base + STRAP_REG(1)); >> + val |= LINK_TRAINING_ENABLE; >> + writel(val, pcie->strap_base + STRAP_REG(1)); >> + >> + return 0; >> +} >> + >> +static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie) >> +{ >> + struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); >> + u32 val; >> + >> + val = readl(pcie->strap_base + STRAP_REG(1)); >> + val &= ~LINK_TRAINING_ENABLE; >> + writel(val, pcie->strap_base + STRAP_REG(1)); >> +} >> + >> +static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie) >> +{ >> + u32 val; >> + >> + val = cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG, >> + IP_REG_I_DBG_STS_0); >> + return val & LINK_COMPLETE; >> +} >> + >> +static const struct cdns_pcie_ops sky1_pcie_ops = { >> + .start_link = sky1_pcie_start_link, >> + .stop_link = sky1_pcie_stop_link, >> + .link_up = sky1_pcie_link_up, >> +}; >> + >> +static int sky1_pcie_probe(struct platform_device *pdev) >> +{ >> + struct cdns_plat_pcie_of_data *reg_off; >> + struct device *dev = &pdev->dev; >> + struct pci_host_bridge *bridge; >> + struct cdns_pcie *cdns_pcie; >> + struct resource_entry *bus; >> + struct cdns_pcie_rc *rc; >> + struct sky1_pcie *pcie; >> + int ret; >> + >> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); >> + if (!pcie) >> + return -ENOMEM; >> + >> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); >> + if (!bridge) >> + return -ENOMEM; >> + >> + ret = sky1_pcie_resource_get(pdev, pcie); >> + if (ret < 0) >> + return -ENXIO; > > return ret; Will change. Best regards, Hans > > - Mani > > -- > மணிவண்ணன் சதாசிவம்