* [PATCH v1 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
2025-07-08 18:48 [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
@ 2025-07-08 18:48 ` Stefano Radaelli
2025-07-09 8:43 ` Krzysztof Kozlowski
2025-07-08 18:48 ` [PATCH v1 2/3] arm64: dts: ti: Add support " Stefano Radaelli
` (2 subsequent siblings)
3 siblings, 1 reply; 14+ messages in thread
From: Stefano Radaelli @ 2025-07-08 18:48 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module
and its carrier boards.
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index bf6003d8fb76..07d2c2ab5150 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -100,6 +100,11 @@ properties:
- const: toradex,verdin-am62p # Verdin AM62P Module
- const: ti,am62p5
+ - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards
+ items:
+ - const: variscite,am62p-var-som
+ - const: ti,am62p5
+
- description: K3 AM642 SoC
items:
- enum:
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
2025-07-08 18:48 ` [PATCH v1 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
@ 2025-07-09 8:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-09 8:43 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
On 08/07/2025 20:48, Stefano Radaelli wrote:
> Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module
> and its carrier boards.
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> index bf6003d8fb76..07d2c2ab5150 100644
> --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> @@ -100,6 +100,11 @@ properties:
> - const: toradex,verdin-am62p # Verdin AM62P Module
> - const: ti,am62p5
>
> + - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards
> + items:
> + - const: variscite,am62p-var-som
SoMs cannot be used alone, at least usually. You miss boards in the list
of compatibles. Look how other variscite boards are made.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-08 18:48 [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
2025-07-08 18:48 ` [PATCH v1 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
@ 2025-07-08 18:48 ` Stefano Radaelli
2025-07-08 21:09 ` Andrew Lunn
` (2 more replies)
2025-07-08 18:48 ` [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board Stefano Radaelli
2025-07-08 23:43 ` [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Rob Herring (Arm)
3 siblings, 3 replies; 14+ messages in thread
From: Stefano Radaelli @ 2025-07-08 18:48 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Add device tree support for the Variscite VAR-SOM-AM62P system on module.
This SOM is designed to be used with various carrier boards.
The module includes:
- AM62Px Sitara MPU processor
- Up to 8GB of DDR4-3733 memory
- eMMC storage memory
- PS6522430 chip as a Power Management Integrated circuit (PMIC)
- Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
- Resistive touch panel interface controller TI TSC2046
- I2C interfaces
Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.
Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++++++++
1 file changed, 379 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
new file mode 100644
index 000000000000..1d4ebc484d55
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for Variscite VAR-SOM-AM62P
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "k3-am62p5.dtsi"
+
+/ {
+ compatible = "variscite,am62p-var-som", "ti,am62p5";
+
+ iw612_pwrseq: iw612_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
+ <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ status = "okay";
+ };
+
+ emmc_pwrseq: pwrseq@0 {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pwrseq_pins>;
+ reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
+ };
+
+ memory@80000000 {
+ /* 8G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000001 0x80000000>;
+ device_type = "memory";
+ bootph-pre-ram;
+ };
+
+ opp-table {
+ /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b500000 0x00 0x00300000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b800000 0x00 0x00100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b900000 0x00 0x00f00000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c800000 0x00 0x00100000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c900000 0x00 0x01e00000>;
+ no-map;
+ };
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ no-map;
+ };
+ };
+
+ vcc_3v3: vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_phy_3v3: regulator-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_phy_3v3";
+ gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ status="okay";
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+ cpsw3g_phy0: ethernet-phy@4 {
+ reg = <4>;
+ compatible = "ethernet-phy-id0283.bc30";
+ reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ };
+};
+
+&cpsw_port1 {
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the SOM PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <&cpsw3g_phy0>;
+ status = "okay";
+};
+
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_pmx0 {
+ emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
+ AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
+ AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
+ AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
+ AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
+ >;
+ };
+
+ main_mmc2_pins_default: main-mmc2-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
+ AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
+ AM62PX_IOPAD(0x011C, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
+ AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
+ AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
+ AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
+ AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
+ AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
+ AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
+ AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
+ AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
+ AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
+ AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
+ AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
+ AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
+ AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
+ AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
+ AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
+ >;
+ bootph-all;
+ };
+
+ main_spi0_pins_default: main_spi0-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
+ AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
+ AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
+ AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
+ >;
+ };
+
+ main_uart5_pins_default: uart5-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
+ AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
+ AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
+ AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
+ >;
+ };
+
+ pinctrl_bt: btgrp {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
+ >;
+ };
+
+ pinctrl_restouch: restouchgrp {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
+ >;
+ };
+
+ pinctrl_wifi: pinctrl-wifi-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
+ AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
+ >;
+ };
+};
+
+&main_spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins_default>;
+ ti,pindir-d0-out-d1-in = <1>;
+
+ /* Resistive touch controller */
+ ads7846@0 {
+ compatible = "ti,ads7846";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_restouch>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <1500000>;
+ pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>;
+ ti,x-min = /bits/ 16 <125>;
+ ti,x-max = /bits/ 16 <4008>;
+ ti,y-min = /bits/ 16 <282>;
+ ti,y-max = /bits/ 16 <3864>;
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+ ti,debounce-max = /bits/ 16 <10>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <1>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ ti,keep-vref-on;
+ wakeup-source;
+ status = "okay";
+ };
+};
+
+&main_uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart5_pins_default>, <&pinctrl_bt>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth_iw61x: bluetooth_iw61x {
+ compatible = "nxp,88w8987-bt";
+ status = "okay";
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <0>;
+ rx-num-evt = <0>;
+};
+
+&mcu_pmx0 {
+ wkup_clkout0_pins_default: wkup_clkout0_pins_default {
+ pinctrl-single,pins = <
+ AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
+ >;
+ };
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ ti,driver-strength-ohm = <50>;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ disable-wp;
+ bootph-all;
+};
+
+/* WIFI */
+&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc2_pins_default>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ disable-wp;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&iw612_pwrseq>;
+ ti,fails-without-test-cd;
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usbss1 {
+ ti,vbus-divider;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-08 18:48 ` [PATCH v1 2/3] arm64: dts: ti: Add support " Stefano Radaelli
@ 2025-07-08 21:09 ` Andrew Lunn
2025-07-09 4:14 ` Vignesh Raghavendra
2025-07-09 8:46 ` Krzysztof Kozlowski
2 siblings, 0 replies; 14+ messages in thread
From: Andrew Lunn @ 2025-07-08 21:09 UTC (permalink / raw)
To: Stefano Radaelli
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
> +&cpsw_port1 {
> + /*
> + * The required RGMII TX and RX 2ns delays are implemented directly
> + * in hardware via passive delay elements on the SOM PCB.
> + * No delay configuration is needed in software via PHY driver.
> + */
> + phy-mode = "rgmii";
> + phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> +};
Thanks for adding the comment. For this bit:
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-08 18:48 ` [PATCH v1 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2025-07-08 21:09 ` Andrew Lunn
@ 2025-07-09 4:14 ` Vignesh Raghavendra
2025-07-09 8:02 ` Stefano Radaelli
2025-07-09 8:46 ` Krzysztof Kozlowski
2 siblings, 1 reply; 14+ messages in thread
From: Vignesh Raghavendra @ 2025-07-09 4:14 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Tero Kristo, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel
On 09/07/25 00:18, Stefano Radaelli wrote:
> Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - AM62Px Sitara MPU processor
> - Up to 8GB of DDR4-3733 memory
> - eMMC storage memory
> - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> - Resistive touch panel interface controller TI TSC2046
> - I2C interfaces
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++++++++
> 1 file changed, 379 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> new file mode 100644
> index 000000000000..1d4ebc484d55
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -0,0 +1,379 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Common dtsi for Variscite VAR-SOM-AM62P
> + *
> + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> + compatible = "variscite,am62p-var-som", "ti,am62p5";
> +
> + iw612_pwrseq: iw612_pwrseq {
No underscore in node names please
> + compatible = "mmc-pwrseq-simple";
> + post-power-on-delay-ms = <100>;
> + power-off-delay-us = <10000>;
> + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + status = "okay";
> + };
> +
> + emmc_pwrseq: pwrseq@0 {
There isnt a reg property to have a unit addresss
> + compatible = "mmc-pwrseq-emmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_pwrseq_pins>;
> + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> + };
> +
> + memory@80000000 {
> + /* 8G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000001 0x80000000>;
> + device_type = "memory";
> + bootph-pre-ram;
> + };
> +
> + opp-table {
> + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + };
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b500000 0x00 0x00300000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> + no-map;
> + };
> +
> + secure_tfa_ddr: tfa@9e780000 {
> + reg = <0x00 0x9e780000 0x00 0x80000>;
> + no-map;
> + };
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> + no-map;
> + };
> + };
> +
> + vcc_3v3: vcc-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vcc_1v8: vcc-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&vcc_3v3>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_phy_3v3: regulator-8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_phy_3v3";
> + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + status="okay";
> + };
> +};
> +
> +&cpsw3g {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_rgmii1_pins_default>;
> +};
> +
> +&cpsw3g_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mdio1_pins_default>;
> + cpsw3g_phy0: ethernet-phy@4 {
> + reg = <4>;
> + compatible = "ethernet-phy-id0283.bc30";
> + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <100000>;
> + };
> +};
> +
> +&cpsw_port1 {
> + /*
> + * The required RGMII TX and RX 2ns delays are implemented directly
> + * in hardware via passive delay elements on the SOM PCB.
> + * No delay configuration is needed in software via PHY driver.
> + */
> + phy-mode = "rgmii";
> + phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> +};
> +
> +&main_i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c2_pins_default>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c3_pins_default>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_pmx0 {
> + emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
Same here
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
> + >;
> + };
> +
> + main_i2c2_pins_default: main-i2c2-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
> + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
> + >;
> + };
> +
> + main_i2c3_pins_default: main-i2c3-pins-default {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
> + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
> + >;
> + };
> +
> + main_mcasp1_pins_default: main-mcasp1-pins-default {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
> + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
> + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
> + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
> + AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
> + >;
> + };
> +
> + main_mdio1_pins_default: main-mdio1-pins-default {
This fails make dtbs_check (node name needs to end in -pins)
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
> + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
> + >;
> + };
> +
> + main_mmc2_pins_default: main-mmc2-pins-default {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
> + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
> + AM62PX_IOPAD(0x011C, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
> + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
> + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
> + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
> + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
> + >;
> + };
> +
> + main_rgmii1_pins_default: main-rgmii1-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
> + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
> + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
> + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
> + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
> + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
> + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
> + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
> + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
> + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
> + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
> + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
> + >;
> + bootph-all;
> + };
> +
> + main_spi0_pins_default: main_spi0-pins-default {
Same here
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
> + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
> + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
> + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
> + >;
> + };
> +
> + main_uart5_pins_default: uart5-pins-default {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
> + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
> + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
> + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
> + >;
> + };
> +
> + pinctrl_bt: btgrp {
More such issues
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
> + >;
> + };
> +
> + pinctrl_restouch: restouchgrp {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
> + >;
> + };
> +
> + pinctrl_wifi: pinctrl-wifi-default {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
> + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
> + >;
> + };
> +};
> +
> +&main_spi0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_spi0_pins_default>;
> + ti,pindir-d0-out-d1-in = <1>;
> +
> + /* Resistive touch controller */
> + ads7846@0 {
> + compatible = "ti,ads7846";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_restouch>;
> + interrupt-parent = <&main_gpio0>;
> + interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
> + spi-max-frequency = <1500000>;
> + pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>;
> + ti,x-min = /bits/ 16 <125>;
> + ti,x-max = /bits/ 16 <4008>;
> + ti,y-min = /bits/ 16 <282>;
> + ti,y-max = /bits/ 16 <3864>;
> + ti,x-plate-ohms = /bits/ 16 <180>;
> + ti,pressure-max = /bits/ 16 <255>;
> + ti,debounce-max = /bits/ 16 <10>;
> + ti,debounce-tol = /bits/ 16 <3>;
> + ti,debounce-rep = /bits/ 16 <1>;
> + ti,settle-delay-usec = /bits/ 16 <150>;
> + ti,keep-vref-on;
> + wakeup-source;
> + status = "okay";
> + };
> +};
> +
> +&main_uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_uart5_pins_default>, <&pinctrl_bt>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth_iw61x: bluetooth_iw61x {
Please run
make dtbs W=1
make CHECK_DTBS=y
and fix all the issues
> + compatible = "nxp,88w8987-bt";
> + status = "okay";
> + };
> +};
> +
> +&mcasp1 {
> + status = "okay";
> + #sound-dai-cells = <0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcasp1_pins_default>;
> +
> + op-mode = <0>; /* MCASP_IIS_MODE */
> + tdm-slots = <2>;
> +
> + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
> + 1 0 2 0
> + 0 0 0 0
> + 0 0 0 0
> + 0 0 0 0
> + >;
> + tx-num-evt = <0>;
> + rx-num-evt = <0>;
> +};
> +
> +&mcu_pmx0 {
> + wkup_clkout0_pins_default: wkup_clkout0_pins_default {
> + pinctrl-single,pins = <
> + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
> + >;
> + };
> +};
> +
> +/* eMMC */
> +&sdhci0 {
> + status = "okay";
> + ti,driver-strength-ohm = <50>;
> + mmc-pwrseq = <&emmc_pwrseq>;
> + disable-wp;
> + bootph-all;
> +};
> +
> +/* WIFI */
> +&sdhci2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mmc2_pins_default>, <&pinctrl_wifi>;
> + bus-width = <4>;
> + disable-wp;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&iw612_pwrseq>;
> + ti,fails-without-test-cd;
> + status = "okay";
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> +};
> +
> +&usbss1 {
> + ti,vbus-divider;
> +};
--
Regards
Vignesh
https://ti.com/opensource
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-09 4:14 ` Vignesh Raghavendra
@ 2025-07-09 8:02 ` Stefano Radaelli
0 siblings, 0 replies; 14+ messages in thread
From: Stefano Radaelli @ 2025-07-09 8:02 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: devicetree, linux-kernel, Nishanth Menon, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
Hello Vignesh,
thank you for your corrections, I completely forgot to compile with
the W=1 flag.
I'll take care of everything,
Best Regards,
Stefano
Il giorno mer 9 lug 2025 alle ore 06:14 Vignesh Raghavendra
<vigneshr@ti.com> ha scritto:
>
>
>
> On 09/07/25 00:18, Stefano Radaelli wrote:
> > Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> > This SOM is designed to be used with various carrier boards.
> >
> > The module includes:
> > - AM62Px Sitara MPU processor
> > - Up to 8GB of DDR4-3733 memory
> > - eMMC storage memory
> > - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> > - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> > - Resistive touch panel interface controller TI TSC2046
> > - I2C interfaces
> >
> > Only SOM-specific peripherals are enabled by default. Carrier board
> > specific interfaces are left disabled to be enabled in the respective
> > carrier board device trees.
> >
> > Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> >
> > Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> > ---
> > arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++++++++
> > 1 file changed, 379 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > new file mode 100644
> > index 000000000000..1d4ebc484d55
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > @@ -0,0 +1,379 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Common dtsi for Variscite VAR-SOM-AM62P
> > + *
> > + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
> > + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/pwm/pwm.h>
> > +#include "k3-am62p5.dtsi"
> > +
> > +/ {
> > + compatible = "variscite,am62p-var-som", "ti,am62p5";
> > +
> > + iw612_pwrseq: iw612_pwrseq {
>
> No underscore in node names please
>
> > + compatible = "mmc-pwrseq-simple";
> > + post-power-on-delay-ms = <100>;
> > + power-off-delay-us = <10000>;
> > + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> > + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> > + status = "okay";
> > + };
> > +
> > + emmc_pwrseq: pwrseq@0 {
>
> There isnt a reg property to have a unit addresss
>
> > + compatible = "mmc-pwrseq-emmc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&emmc_pwrseq_pins>;
> > + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + memory@80000000 {
> > + /* 8G RAM */
> > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> > + <0x00000008 0x80000000 0x00000001 0x80000000>;
> > + device_type = "memory";
> > + bootph-pre-ram;
> > + };
> > +
> > + opp-table {
> > + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> > + opp-1400000000 {
> > + opp-hz = /bits/ 64 <1400000000>;
> > + opp-supported-hw = <0x01 0x0004>;
> > + clock-latency-ns = <6000000>;
> > + };
> > + };
> > +
> > + reserved_memory: reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b500000 0x00 0x00300000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> > + no-map;
> > + };
> > +
> > + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> > + no-map;
> > + };
> > +
> > + secure_tfa_ddr: tfa@9e780000 {
> > + reg = <0x00 0x9e780000 0x00 0x80000>;
> > + no-map;
> > + };
> > +
> > + secure_ddr: optee@9e800000 {
> > + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> > + no-map;
> > + };
> > + };
> > +
> > + vcc_3v3: vcc-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc_3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + vcc_1v8: vcc-1v8 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc_1v8";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + vin-supply = <&vcc_3v3>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + vdd_phy_3v3: regulator-8 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vdd_phy_3v3";
> > + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-always-on;
> > + status="okay";
> > + };
> > +};
> > +
> > +&cpsw3g {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_rgmii1_pins_default>;
> > +};
> > +
> > +&cpsw3g_mdio {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_mdio1_pins_default>;
> > + cpsw3g_phy0: ethernet-phy@4 {
> > + reg = <4>;
> > + compatible = "ethernet-phy-id0283.bc30";
> > + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> > + reset-assert-us = <10000>;
> > + reset-deassert-us = <100000>;
> > + };
> > +};
> > +
> > +&cpsw_port1 {
> > + /*
> > + * The required RGMII TX and RX 2ns delays are implemented directly
> > + * in hardware via passive delay elements on the SOM PCB.
> > + * No delay configuration is needed in software via PHY driver.
> > + */
> > + phy-mode = "rgmii";
> > + phy-handle = <&cpsw3g_phy0>;
> > + status = "okay";
> > +};
> > +
> > +&main_i2c2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_i2c2_pins_default>;
> > + clock-frequency = <400000>;
> > + status = "okay";
> > +};
> > +
> > +&main_i2c3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_i2c3_pins_default>;
> > + clock-frequency = <400000>;
> > + status = "okay";
> > +};
> > +
> > +&main_pmx0 {
> > + emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
>
> Same here
>
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
> > + >;
> > + };
> > +
> > + main_i2c2_pins_default: main-i2c2-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
> > + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
> > + >;
> > + };
> > +
> > + main_i2c3_pins_default: main-i2c3-pins-default {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
> > + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
> > + >;
> > + };
> > +
> > + main_mcasp1_pins_default: main-mcasp1-pins-default {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
> > + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
> > + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
> > + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
> > + AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
> > + >;
> > + };
> > +
> > + main_mdio1_pins_default: main-mdio1-pins-default {
>
> This fails make dtbs_check (node name needs to end in -pins)
>
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
> > + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
> > + >;
> > + };
> > +
> > + main_mmc2_pins_default: main-mmc2-pins-default {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
> > + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
> > + AM62PX_IOPAD(0x011C, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
> > + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
> > + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
> > + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
> > + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
> > + >;
> > + };
> > +
> > + main_rgmii1_pins_default: main-rgmii1-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
> > + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
> > + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
> > + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
> > + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
> > + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
> > + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
> > + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
> > + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
> > + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
> > + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
> > + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
> > + >;
> > + bootph-all;
> > + };
> > +
> > + main_spi0_pins_default: main_spi0-pins-default {
>
> Same here
>
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
> > + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
> > + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
> > + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
> > + >;
> > + };
> > +
> > + main_uart5_pins_default: uart5-pins-default {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
> > + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
> > + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
> > + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
> > + >;
> > + };
> > +
> > + pinctrl_bt: btgrp {
>
> More such issues
>
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
> > + >;
> > + };
> > +
> > + pinctrl_restouch: restouchgrp {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
> > + >;
> > + };
> > +
> > + pinctrl_wifi: pinctrl-wifi-default {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
> > + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
> > + >;
> > + };
> > +};
> > +
> > +&main_spi0 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_spi0_pins_default>;
> > + ti,pindir-d0-out-d1-in = <1>;
> > +
> > + /* Resistive touch controller */
> > + ads7846@0 {
> > + compatible = "ti,ads7846";
> > + reg = <0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_restouch>;
> > + interrupt-parent = <&main_gpio0>;
> > + interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
> > + spi-max-frequency = <1500000>;
> > + pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>;
> > + ti,x-min = /bits/ 16 <125>;
> > + ti,x-max = /bits/ 16 <4008>;
> > + ti,y-min = /bits/ 16 <282>;
> > + ti,y-max = /bits/ 16 <3864>;
> > + ti,x-plate-ohms = /bits/ 16 <180>;
> > + ti,pressure-max = /bits/ 16 <255>;
> > + ti,debounce-max = /bits/ 16 <10>;
> > + ti,debounce-tol = /bits/ 16 <3>;
> > + ti,debounce-rep = /bits/ 16 <1>;
> > + ti,settle-delay-usec = /bits/ 16 <150>;
> > + ti,keep-vref-on;
> > + wakeup-source;
> > + status = "okay";
> > + };
> > +};
> > +
> > +&main_uart5 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_uart5_pins_default>, <&pinctrl_bt>;
> > + uart-has-rtscts;
> > + status = "okay";
> > +
> > + bluetooth_iw61x: bluetooth_iw61x {
>
> Please run
> make dtbs W=1
> make CHECK_DTBS=y
>
> and fix all the issues
>
> > + compatible = "nxp,88w8987-bt";
> > + status = "okay";
> > + };
> > +};
> > +
> > +&mcasp1 {
> > + status = "okay";
> > + #sound-dai-cells = <0>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_mcasp1_pins_default>;
> > +
> > + op-mode = <0>; /* MCASP_IIS_MODE */
> > + tdm-slots = <2>;
> > +
> > + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
> > + 1 0 2 0
> > + 0 0 0 0
> > + 0 0 0 0
> > + 0 0 0 0
> > + >;
> > + tx-num-evt = <0>;
> > + rx-num-evt = <0>;
> > +};
> > +
> > +&mcu_pmx0 {
> > + wkup_clkout0_pins_default: wkup_clkout0_pins_default {
> > + pinctrl-single,pins = <
> > + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
> > + >;
> > + };
> > +};
> > +
> > +/* eMMC */
> > +&sdhci0 {
> > + status = "okay";
> > + ti,driver-strength-ohm = <50>;
> > + mmc-pwrseq = <&emmc_pwrseq>;
> > + disable-wp;
> > + bootph-all;
> > +};
> > +
> > +/* WIFI */
> > +&sdhci2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&main_mmc2_pins_default>, <&pinctrl_wifi>;
> > + bus-width = <4>;
> > + disable-wp;
> > + non-removable;
> > + keep-power-in-suspend;
> > + mmc-pwrseq = <&iw612_pwrseq>;
> > + ti,fails-without-test-cd;
> > + status = "okay";
> > +};
> > +
> > +&usbss0 {
> > + ti,vbus-divider;
> > +};
> > +
> > +&usbss1 {
> > + ti,vbus-divider;
> > +};
>
> --
> Regards
> Vignesh
> https://ti.com/opensource
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-08 18:48 ` [PATCH v1 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2025-07-08 21:09 ` Andrew Lunn
2025-07-09 4:14 ` Vignesh Raghavendra
@ 2025-07-09 8:46 ` Krzysztof Kozlowski
2025-07-09 17:16 ` Stefano Radaelli
2 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-09 8:46 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
On 08/07/2025 20:48, Stefano Radaelli wrote:
> Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - AM62Px Sitara MPU processor
> - Up to 8GB of DDR4-3733 memory
> - eMMC storage memory
> - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> - Resistive touch panel interface controller TI TSC2046
> - I2C interfaces
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++++++++
> 1 file changed, 379 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> new file mode 100644
> index 000000000000..1d4ebc484d55
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -0,0 +1,379 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Common dtsi for Variscite VAR-SOM-AM62P
> + *
> + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> + compatible = "variscite,am62p-var-som", "ti,am62p5";
> +
> + iw612_pwrseq: iw612_pwrseq {
Follow DTS coding style. This applies to multiple places.
Also:
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "mmc-pwrseq-simple";
> + post-power-on-delay-ms = <100>;
> + power-off-delay-us = <10000>;
> + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + status = "okay";
Why? Drop.
> + };
> +
> + emmc_pwrseq: pwrseq@0 {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
> + compatible = "mmc-pwrseq-emmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_pwrseq_pins>;
> + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> + };
> +
> + memory@80000000 {
> + /* 8G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000001 0x80000000>;
> + device_type = "memory";
> + bootph-pre-ram;
> + };
> +
> + opp-table {
> + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + };
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b500000 0x00 0x00300000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> + no-map;
> + };
> +
> + secure_tfa_ddr: tfa@9e780000 {
> + reg = <0x00 0x9e780000 0x00 0x80000>;
> + no-map;
> + };
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> + no-map;
> + };
> + };
> +
> + vcc_3v3: vcc-3v3 {
Please use name for all fixed regulators which matches current format
recommendation: 'regulator-[0-9]v[0-9]'
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml?h=v6.11-rc1#n46
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-09 8:46 ` Krzysztof Kozlowski
@ 2025-07-09 17:16 ` Stefano Radaelli
2025-07-10 6:48 ` Krzysztof Kozlowski
0 siblings, 1 reply; 14+ messages in thread
From: Stefano Radaelli @ 2025-07-09 17:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Hello Krzysztof,
thank you for your corrections, I completely forgot to compile with
the W=1 flag.
I'll take care of everything,
Best Regards,
Stefano
Il giorno mer 9 lug 2025 alle ore 10:46 Krzysztof Kozlowski
<krzk@kernel.org> ha scritto:
>
> On 08/07/2025 20:48, Stefano Radaelli wrote:
> > Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> > This SOM is designed to be used with various carrier boards.
> >
> > The module includes:
> > - AM62Px Sitara MPU processor
> > - Up to 8GB of DDR4-3733 memory
> > - eMMC storage memory
> > - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> > - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> > - Resistive touch panel interface controller TI TSC2046
> > - I2C interfaces
> >
> > Only SOM-specific peripherals are enabled by default. Carrier board
> > specific interfaces are left disabled to be enabled in the respective
> > carrier board device trees.
> >
> > Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> >
> > Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> > ---
> > arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++++++++
> > 1 file changed, 379 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > new file mode 100644
> > index 000000000000..1d4ebc484d55
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > @@ -0,0 +1,379 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Common dtsi for Variscite VAR-SOM-AM62P
> > + *
> > + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
> > + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/pwm/pwm.h>
> > +#include "k3-am62p5.dtsi"
> > +
> > +/ {
> > + compatible = "variscite,am62p-var-som", "ti,am62p5";
> > +
> > + iw612_pwrseq: iw612_pwrseq {
>
> Follow DTS coding style. This applies to multiple places.
>
> Also:
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
>
> > + compatible = "mmc-pwrseq-simple";
> > + post-power-on-delay-ms = <100>;
> > + power-off-delay-us = <10000>;
> > + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> > + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> > + status = "okay";
>
> Why? Drop.
>
> > + };
> > +
> > + emmc_pwrseq: pwrseq@0 {
>
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on
> distro packages for dtschema and be sure you are using the latest
> released dtschema.
>
> > + compatible = "mmc-pwrseq-emmc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&emmc_pwrseq_pins>;
> > + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + memory@80000000 {
> > + /* 8G RAM */
> > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> > + <0x00000008 0x80000000 0x00000001 0x80000000>;
> > + device_type = "memory";
> > + bootph-pre-ram;
> > + };
> > +
> > + opp-table {
> > + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> > + opp-1400000000 {
> > + opp-hz = /bits/ 64 <1400000000>;
> > + opp-supported-hw = <0x01 0x0004>;
> > + clock-latency-ns = <6000000>;
> > + };
> > + };
> > +
> > + reserved_memory: reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b500000 0x00 0x00300000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> > + no-map;
> > + };
> > +
> > + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> > + no-map;
> > + };
> > +
> > + secure_tfa_ddr: tfa@9e780000 {
> > + reg = <0x00 0x9e780000 0x00 0x80000>;
> > + no-map;
> > + };
> > +
> > + secure_ddr: optee@9e800000 {
> > + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> > + no-map;
> > + };
> > + };
> > +
> > + vcc_3v3: vcc-3v3 {
>
> Please use name for all fixed regulators which matches current format
> recommendation: 'regulator-[0-9]v[0-9]'
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml?h=v6.11-rc1#n46
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-07-09 17:16 ` Stefano Radaelli
@ 2025-07-10 6:48 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-10 6:48 UTC (permalink / raw)
To: Stefano Radaelli
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
On 09/07/2025 19:16, Stefano Radaelli wrote:
> Hello Krzysztof,
>
> thank you for your corrections, I completely forgot to compile with
> the W=1 flag.
Don't top post. I did not ask to compile with W=1, but check your dtbs.
Please read carefully instructions.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board
2025-07-08 18:48 [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
2025-07-08 18:48 ` [PATCH v1 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
2025-07-08 18:48 ` [PATCH v1 2/3] arm64: dts: ti: Add support " Stefano Radaelli
@ 2025-07-08 18:48 ` Stefano Radaelli
2025-07-08 21:10 ` Andrew Lunn
2025-07-09 8:45 ` Krzysztof Kozlowski
2025-07-08 23:43 ` [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Rob Herring (Arm)
3 siblings, 2 replies; 14+ messages in thread
From: Stefano Radaelli @ 2025-07-08 18:48 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Add device tree support for the Variscite Symphony carrier board with
the VAR-SOM-AM62P system on module.
The Symphony board includes
- uSD Card support
- USB ports and OTG
- Additional Gigabit Ethernet interface
- Uart interfaces
- OV5640 Camera support
- GPIO Expander
- CAN, I2C and general purpose interfaces
Link: https://www.variscite.it/product/single-board-computers/symphony-board/
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
.../dts/ti/k3-am62p5-var-som-symphony.dts | 545 ++++++++++++++++++
1 file changed, 545 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
new file mode 100644
index 000000000000..ec6bdd28d57f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Variscite Symphony carrier board for VAR-SOM-AM62P
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5-var-som.dtsi"
+
+/ {
+ model = "Variscite VAR-SOM-AM62P on Symphony-Board";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ mmc2 = &sdhci2;
+ serial0 = &main_uart0;
+ serial2 = &main_uart2;
+ serial5 = &main_uart5;
+ serial6 = &main_uart6;
+ spi5 = &main_spi2;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ clk_ov5640_fixed: clock {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ status = "okay";
+ back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+ };
+
+ home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+ };
+
+ menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ heartbeat {
+ label = "Heartbeat";
+ linux,default-trigger = "heartbeat";
+ gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ ov5640_buf_en: ov5640-buf-en {
+ compatible = "regulator-fixed";
+ regulator-name = "ov5640_buf_en";
+ gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ status="okay";
+ };
+
+ transceiver1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ vdd_mmc1: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "sd_ext_rst";
+ vin-supply = <&vdd_mmc1_int>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ vdd_mmc1_int: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "sd_int_rst";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_mmc1_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ vdd_sd_dv: regulator-3 {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_sd_vio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ bootph-all;
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>,
+ <&main_rgmii2_pins_default>;
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy1: ethernet-phy@5 {
+ reg = <5>;
+ compatible = "ethernet-phy-id0283.bc30";
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ };
+};
+
+&cpsw_port2 {
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the Symphony PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <&cpsw3g_phy1>;
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&mailbox0_cluster0 {
+ mbox_r5_0: mbox-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ mbox_mcu_r5_0: mbox-mcu-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&main_i2c0{
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+ powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ov5640_pins_default>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ /* GPIO expander */
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pca9534_irq_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ status = "okay";
+
+ usb3_sel_hog {
+ gpio-hog;
+ gpios = <4 0>;
+ output-low;
+ line-name = "usb3_sel";
+ };
+
+ eth_som_vselect_hog {
+ gpio-hog;
+ gpios = <6 0>;
+ output-low;
+ line-name = "eth-vselect";
+ };
+
+ eth_mdio_enable_hog {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ line-name = "eth-mdio-enable";
+ };
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* DS1337 RTC module */
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ status = "okay";
+ };
+};
+
+&main_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&transceiver1>;
+};
+
+&main_pmx0 {
+ extcon_pins_default: extcon-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */
+ AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
+ AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */
+ >;
+ bootph-all;
+ };
+
+ main_mcan0_pins_default: main-mcan0-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */
+ AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */
+ AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */
+ AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */
+ AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */
+ AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */
+ AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
+ AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+
+ main_rgmii2_pins_default: main-rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */
+ AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */
+ AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */
+ AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */
+ AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */
+ AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */
+ AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */
+ AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */
+ AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */
+ AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */
+ AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */
+ AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */
+ >;
+ };
+
+ main_spi2_pins_default: main_spi2-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */
+ AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */
+ AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */
+ AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
+ AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ main_uart2_pins_default: main-uart2-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD */
+ AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */
+ >;
+ };
+
+ main_uart6_pins_default: main-uart6-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_RXD */
+ AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */
+ >;
+ };
+
+ main_usb1_pins_default: main-usb1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */
+ >;
+ };
+
+ ov5640_pins_default: ov5640-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */
+ AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */
+ AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */
+ >;
+ };
+
+ pca9534_irq_default: pca9534_irq_default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */
+ >;
+ };
+
+ vdd_mmc1_pins_default: vdd-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */
+ AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */
+ >;
+ bootph-all;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */
+ >;
+ bootph-all;
+ };
+};
+
+&main_spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi2_pins_default>;
+ ti,pindir-d0-out-d1-in = <1>;
+ cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>;
+};
+
+&main_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart1 {
+ /* Main UART1 is used by TIFS firmware */
+ status = "reserved";
+};
+
+&main_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart2_pins_default>;
+ status = "okay";
+};
+
+&main_uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart6_pins_default>;
+ status = "okay";
+};
+
+&mcu_gpio0 {
+ status = "reserved";
+};
+
+&mcu_gpio_intr {
+ status = "reserved";
+};
+
+&mcu_r5fss0 {
+ status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ disable-wp;
+ status="okay";
+ bootph-all;
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&usb0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usb-role-switch;
+ status="okay";
+
+ port@0 {
+ reg = <0>;
+
+ typec_hs: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ status="okay";
+};
+
+&usbss0 {
+ status = "okay";
+
+ connector {
+ compatible = "gpio-usb-b-connector","usb-c-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&extcon_pins_default>;
+ label = "USB-C";
+ id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+ };
+};
+
+&usbss1 {
+ status = "okay";
+};
+
+&wkup_r5fss0 {
+ status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
+ memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+ <&wkup_r5fss0_core0_memory_region>;
+};
+
+&wkup_rtc0 {
+ status = "disabled";
+};
+
+&wkup_rti0 {
+ /* WKUP RTI0 is used by DM firmware */
+ status = "reserved";
+};
+
+&wkup_uart0 {
+ /* WKUP UART0 is used by DM firmware */
+ status = "reserved";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board
2025-07-08 18:48 ` [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board Stefano Radaelli
@ 2025-07-08 21:10 ` Andrew Lunn
2025-07-09 8:45 ` Krzysztof Kozlowski
1 sibling, 0 replies; 14+ messages in thread
From: Andrew Lunn @ 2025-07-08 21:10 UTC (permalink / raw)
To: Stefano Radaelli
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
> +&cpsw_port2 {
> + /*
> + * The required RGMII TX and RX 2ns delays are implemented directly
> + * in hardware via passive delay elements on the Symphony PCB.
> + * No delay configuration is needed in software via PHY driver.
> + */
> + phy-mode = "rgmii";
> + phy-handle = <&cpsw3g_phy1>;
> + status = "okay";
> +};
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board
2025-07-08 18:48 ` [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board Stefano Radaelli
2025-07-08 21:10 ` Andrew Lunn
@ 2025-07-09 8:45 ` Krzysztof Kozlowski
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-09 8:45 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
On 08/07/2025 20:48, Stefano Radaelli wrote:
> Add device tree support for the Variscite Symphony carrier board with
> the VAR-SOM-AM62P system on module.
>
> The Symphony board includes
> - uSD Card support
> - USB ports and OTG
> - Additional Gigabit Ethernet interface
> - Uart interfaces
> - OV5640 Camera support
> - GPIO Expander
> - CAN, I2C and general purpose interfaces
>
> Link: https://www.variscite.it/product/single-board-computers/symphony-board/
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> .../dts/ti/k3-am62p5-var-som-symphony.dts | 545 ++++++++++++++++++
> 1 file changed, 545 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
> new file mode 100644
> index 000000000000..ec6bdd28d57f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
> @@ -0,0 +1,545 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Variscite Symphony carrier board for VAR-SOM-AM62P
> + *
> + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62p5-var-som.dtsi"
> +
> +/ {
> + model = "Variscite VAR-SOM-AM62P on Symphony-Board";
Missing compatible.
> +
> + aliases {
> + ethernet0 = &cpsw_port1;
> + ethernet1 = &cpsw_port2;
> + mmc0 = &sdhci0;
> + mmc1 = &sdhci1;
> + mmc2 = &sdhci2;
> + serial0 = &main_uart0;
> + serial2 = &main_uart2;
> + serial5 = &main_uart5;
> + serial6 = &main_uart6;
> + spi5 = &main_spi2;
> + usb0 = &usb0;
> + usb1 = &usb1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "console=ttyS0,115200n8 earlycon=ns16550a,mmio32,0x02800000";
Drop bootargs. It duplicates stdout-path and introduces debugging
earlycon. Mainline usage should not be debugging one.
> + };
> +
> + clk_ov5640_fixed: clock {
Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + status = "okay";
Why? Drop.
> + back {
Never checked/tested. I finish my review here. You have same issues,
like this and earlier one, in other places as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board
2025-07-08 18:48 [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
` (2 preceding siblings ...)
2025-07-08 18:48 ` [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board Stefano Radaelli
@ 2025-07-08 23:43 ` Rob Herring (Arm)
3 siblings, 0 replies; 14+ messages in thread
From: Rob Herring (Arm) @ 2025-07-08 23:43 UTC (permalink / raw)
To: Stefano Radaelli
Cc: Vignesh Raghavendra, Conor Dooley, linux-arm-kernel,
Nishanth Menon, linux-kernel, devicetree, Tero Kristo,
Krzysztof Kozlowski
On Tue, 08 Jul 2025 20:48:32 +0200, Stefano Radaelli wrote:
> This patch series adds support for the Variscite VAR-SOM-AM62P system on module
> and the Symphony carrier board.
>
> The VAR-SOM-AM62P is a compact SOM based on the TI AM62P Sitara processor,
> featuring up to 8GB DDR4 memory, eMMC storage, Gigabit Ethernet, and various
> peripheral interfaces. The Symphony board is a feature-rich carrier board that
> showcases the SOM capabilities.
>
> The series includes:
> - Device tree bindings documentation
> - SOM device tree with common peripherals
> - Symphony carrier board device tree with board-specific features
>
> The implementation follows the standard SOM + carrier board pattern where the
> SOM dtsi contains only peripherals mounted on the module, while carrier-specific
> interfaces are enabled in the board dts.
>
> Tested on VAR-SOM-AM62P with Symphony carrier board.
>
> Stefano Radaelli (3):
> dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
> arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
> arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board
>
> .../devicetree/bindings/arm/ti/k3.yaml | 5 +
> .../dts/ti/k3-am62p5-var-som-symphony.dts | 545 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 379 ++++++++++++
> 3 files changed, 929 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>
>
> base-commit: d7b8f8e20813f0179d8ef519541a3527e7661d3a
> prerequisite-patch-id: 7e8493f8ed01ee319f827119ffdac7531afbbc4d
> --
> 2.43.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit d7b8f8e20813f0179d8ef519541a3527e7661d3a
Deps: looking for dependencies matching 1 patch-ids
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/ti/' for 20250708184841.72933-1-stefano.radaelli21@gmail.com:
ti,pindir-d0-out-d1-in: size (4) error for type flag
ti,pindir-d0-out-d1-in: size (4) error for type flag
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: / (variscite,am62p-var-som): pwrseq@0: 'anyOf' conditional failed, one must be fixed:
'reg' is a required property
'ranges' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: pinctrl@4084000 (pinctrl-single): 'wkup_clkout0_pins_default' does not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: pinctrl@f4000 (pinctrl-single): 'btgrp', 'extcon-pins-default', 'main-i2c0-pins-default', 'main-i2c1-pins-default', 'main-i2c3-pins-default', 'main-mcan0-pins-default', 'main-mcasp1-pins-default', 'main-mdio1-pins-default', 'main-mmc1-pins-default', 'main-mmc2-pins-default', 'main-rgmii2-pins-default', 'main-uart2-pins-default', 'main-uart6-pins-default', 'main-usb1-pins-default', 'main_spi0-pins-default', 'main_spi2-pins-default', 'ov5640-pins-default', 'pca9534_irq_default', 'pinctrl-wifi-default', 'pinmux_emmc_pwrseq_pins', 'restouchgrp', 'uart5-pins-default', 'vdd-mmc1-pins-default', 'vdd-sd-dv-pins-default' do not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: serial@2850000 (ti,am64-uart): Unevaluated properties are not allowed ('bluetooth_iw61x' was unexpected)
from schema $id: http://devicetree.org/schemas/serial/8250_omap.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: bluetooth_iw61x (nxp,88w8987-bt): $nodename:0: 'bluetooth_iw61x' does not match '^bluetooth(@.*)?$'
from schema $id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: camera@3c (ovti,ov5640): 'AVDD-supply' is a required property
from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: camera@3c (ovti,ov5640): 'DVDD-supply' is a required property
from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: camera@3c (ovti,ov5640): 'DOVDD-supply' is a required property
from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: gpio@20 (nxp,pca9534): 'eth_mdio_enable_hog', 'eth_som_vselect_hog', 'usb3_sel_hog' do not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb3_sel_hog: $nodename:0: 'usb3_sel_hog' does not match '-hog(-[0-9]+)?$'
from schema $id: http://devicetree.org/schemas/gpio/gpio-hog.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: eth_som_vselect_hog: $nodename:0: 'eth_som_vselect_hog' does not match '-hog(-[0-9]+)?$'
from schema $id: http://devicetree.org/schemas/gpio/gpio-hog.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: eth_mdio_enable_hog: $nodename:0: 'eth_mdio_enable_hog' does not match '-hog(-[0-9]+)?$'
from schema $id: http://devicetree.org/schemas/gpio/gpio-hog.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: spi@20100000 (ti,am654-mcspi): ti,pindir-d0-out-d1-in: 1 is not of type 'boolean'
from schema $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: spi@20100000 (ti,am654-mcspi): Unevaluated properties are not allowed ('ti,pindir-d0-out-d1-in' was unexpected)
from schema $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: spi@20120000 (ti,am654-mcspi): ti,pindir-d0-out-d1-in: 1 is not of type 'boolean'
from schema $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: spi@20120000 (ti,am654-mcspi): Unevaluated properties are not allowed ('ti,pindir-d0-out-d1-in' was unexpected)
from schema $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb@f900000 (ti,am62-usb): 'connector' does not match any of the regexes: '^pinctrl-[0-9]+$', '^usb@[0-9a-f]+$'
from schema $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb@f900000 (ti,am62-usb): usb@31000000:port@0:reg:0:0: 0 is less than the minimum of 1
from schema $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb@f900000 (ti,am62-usb): usb@31000000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dr_mode', 'maximum-speed', 'port@0', 'snps,usb2-gadget-lpm-disable', 'snps,usb2-lpm-disable', 'usb-role-switch' were unexpected)
from schema $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb@31000000 (snps,dwc3): port@0:reg:0:0: 0 is less than the minimum of 1
from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: usb@31000000 (snps,dwc3): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dr_mode', 'maximum-speed', 'port@0', 'snps,usb2-gadget-lpm-disable', 'snps,usb2-lpm-disable', 'usb-role-switch' were unexpected)
from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: connector (gpio-usb-b-connector): compatible: 'oneOf' conditional failed, one must be fixed:
['gpio-usb-b-connector', 'usb-c-connector'] is too long
'gpio-usb-b-connector' is not one of ['usb-a-connector', 'usb-b-connector', 'usb-c-connector']
'samsung,usb-connector-11pin' was expected
'usb-b-connector' was expected
from schema $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: gpio-keys (gpio-keys): 'back', 'home', 'menu' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/input/gpio-keys.yaml#
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dtb: gpio-leds (gpio-leds): 'heartbeat' does not match any of the regexes: '(^led-[0-9a-f]$|led)', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/leds/leds-gpio.yaml#
^ permalink raw reply [flat|nested] 14+ messages in thread