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Fri, 09 Oct 2026 03:48:20 -0700 (PDT) X-Received: by 2002:a05:6a00:3403:b0:890:b4c2:d7e8 with SMTP id d2e1a72fcca58-897c79e0cf1mr1408225b3a.33.1791542899607; Fri, 09 Oct 2026 03:48:19 -0700 (PDT) Received: from [10.204.78.217] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c3ecb01dsm712832b3a.36.2026.10.09.03.48.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Oct 2026 03:48:19 -0700 (PDT) Message-ID: <6e7779bc-89db-4ed9-b5b5-bff1dfd968b5@oss.qualcomm.com> Date: Fri, 9 Oct 2026 16:18:10 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: dts: qcom: kaanapali: Add DisplayPort controller To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Yongxing Mou , Yuanjie Yang , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Mahadevan P , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261005-kaanapali_dp-v1-0-6faeac3a6d59@oss.qualcomm.com> <20261005-kaanapali_dp-v1-3-6faeac3a6d59@oss.qualcomm.com> Content-Language: en-US From: Balaji Kalkonda In-Reply-To: Content-Type: text/plain; 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>> #phy-cells = <1>; >> >> + mode-switch; > Not mentioned in the commit message. > >> orientation-switch; >> >> status = "disabled"; >> @@ -3851,6 +3854,86 @@ mdss_dsi0_phy: phy@9ac1000 { >> >> status = "disabled"; >> }; >> + >> + mdss_dp0: displayport-controller@9ad2000 { >> + compatible = "qcom,kaanapali-dp"; >> + reg = <0x0 0x09ad2000 0x0 0x10c>, >> + <0x0 0x09ad2200 0x0 0xc8>, >> + <0x0 0x09ad3000 0x0 0x78>, >> + <0x0 0x09ad4000 0x0 0xa0>; >> + >> + interrupts-extended = <&mdss 12>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >> + > Please define all pixel clocks that are used by the DP controller. Is it > not MST-capable? > >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; >> + assigned-clock-parents = >> + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > Don't break the line here. > >> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + >> + power-domains = <&rpmhpd RPMHPD_MX>; > MMCX. If you need to cast a vote on MX domain too, add second entry to > the power domains and handle it in the driver. > >> + >> + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; >> + phy-names = "dp"; >> + >> + #sound-dai-cells = <0>; >> + >> + status = "disabled"; >> + Hi Dmitry, Thanks for reviewing. I'll address all these comments in v2. Thanks, Balaji