From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Jessica Zhang <jesszhan0024@gmail.com>,
Dan Carpenter <dan.carpenter@linaro.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 2/6] dt-bindings: display/msm: gpu: Document A612 GPU
Date: Fri, 14 Nov 2025 17:28:18 +0530 [thread overview]
Message-ID: <6ebe07ad-cbfe-47e2-99ee-06ad7670e699@oss.qualcomm.com> (raw)
In-Reply-To: <20251110-wise-lurking-roadrunner-f0cec3@kuoka>
On 11/10/2025 1:18 PM, Krzysztof Kozlowski wrote:
> On Fri, Nov 07, 2025 at 02:20:07AM +0530, Akhil P Oommen wrote:
>> A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit)
>> which replaces GMU. But it doesn't do clock or voltage scaling. So we
>> need the gpu core clock in the GPU node along with the power domain to
>> do clock and voltage scaling from the kernel. Update the bindings to
>> describe this GPU.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/display/msm/gpu.yaml | 32 ++++++++++++++++++++--
>> 1 file changed, 30 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> index 826aafdcc20b..a6bbc88e6a24 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> @@ -45,11 +45,11 @@ properties:
>> - const: amd,imageon
>>
>> clocks:
>> - minItems: 2
>> + minItems: 1
>> maxItems: 7
>>
>> clock-names:
>> - minItems: 2
>> + minItems: 1
>> maxItems: 7
>>
>> reg:
>> @@ -387,6 +387,34 @@ allOf:
>> required:
>> - clocks
>> - clock-names
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,adreno-612.0
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: GPU Core clock
>> +
>> + clock-names:
>> + items:
>> + - const: core
>> +
>> + reg:
>> + items:
>> + - description: GPU Reg memory
>> +
>> + reg-names:
>> + items:
>> + - const: kgsl_3d0_reg_memory
>
> What happened with the second entry? Please describe the hardware
> COMPLETELY (see writing bindings doc).
We can describe cx_mem and cx_dbgc too here. Then it matches the common
schema described at the top of this file. In that case, do we need to
re-describe it here or we can just remove both reg and reg-names
properties here?
-Akhil.
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2025-11-14 11:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-06 20:50 [PATCH v2 0/6] Support for Adreno 612 GPU - Respin Akhil P Oommen
2025-11-06 20:50 ` [PATCH v2 1/6] drm/msm/a6xx: Add support for Adreno 612 Akhil P Oommen
2025-11-07 8:58 ` Konrad Dybcio
2025-11-11 15:10 ` Akhil P Oommen
2025-11-12 9:59 ` Konrad Dybcio
2025-11-06 20:50 ` [PATCH v2 2/6] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
2025-11-10 7:48 ` Krzysztof Kozlowski
2025-11-14 11:58 ` Akhil P Oommen [this message]
2025-11-06 20:50 ` [PATCH v2 3/6] dt-bindings: display/msm/rgmu: Document A612 RGMU Akhil P Oommen
2025-11-10 7:51 ` Krzysztof Kozlowski
2025-11-11 14:51 ` Akhil P Oommen
2025-11-13 8:11 ` Krzysztof Kozlowski
2025-11-14 12:00 ` Akhil P Oommen
2025-11-14 12:08 ` Akhil P Oommen
2025-11-14 12:16 ` Krzysztof Kozlowski
2025-11-06 20:50 ` [PATCH v2 4/6] arm64: dts: qcom: sm6150: add the GPU SMMU node Akhil P Oommen
2025-11-06 20:50 ` [PATCH v2 5/6] arm64: dts: qcom: sm6150: Add gpu and rgmu nodes Akhil P Oommen
2025-11-07 9:01 ` Konrad Dybcio
2025-11-10 10:42 ` Akhil P Oommen
2025-11-06 20:50 ` [PATCH v2 6/6] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
2025-11-07 8:52 ` [PATCH v2 0/6] Support for Adreno 612 GPU - Respin Konrad Dybcio
2025-11-10 10:46 ` Akhil P Oommen
2025-11-10 14:34 ` Rob Herring (Arm)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6ebe07ad-cbfe-47e2-99ee-06ad7670e699@oss.qualcomm.com \
--to=akhilpo@oss.qualcomm.com \
--cc=abhinav.kumar@linux.dev \
--cc=airlied@gmail.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=dan.carpenter@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=jesszhan0024@gmail.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=krzk@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lumag@kernel.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=marijn.suijten@somainline.org \
--cc=mripard@kernel.org \
--cc=robh@kernel.org \
--cc=robin.clark@oss.qualcomm.com \
--cc=sean@poorly.run \
--cc=simona@ffwll.ch \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).