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Wed, 25 Oct 2023 08:28:11 -0700 (PDT) Received: from [192.168.1.212] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g24-20020a37e218000000b007671b599cf5sm4280080qki.40.2023.10.25.08.28.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Oct 2023 08:28:10 -0700 (PDT) Message-ID: <6f145485-c330-4a89-9e5a-af35d0b72e21@linaro.org> Date: Wed, 25 Oct 2023 18:28:04 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] drm/fourcc: Add drm/vs tiled modifiers Content-Language: en-GB To: Keith Zhao , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org Cc: Krzysztof Kozlowski , Sumit Semwal , Emil Renner Berthing , Shengyang Chen , Conor Dooley , Albert Ou , Thomas Zimmermann , Maxime Ripard , Jagan Teki , Rob Herring , Chris Morgan , Paul Walmsley , Bjorn Andersson , Changhuang Liang , Jack Zhu , Palmer Dabbelt , Shawn Guo , christian.koenig@amd.com References: <20231025103957.3776-1-keith.zhao@starfivetech.com> <20231025103957.3776-4-keith.zhao@starfivetech.com> From: Dmitry Baryshkov In-Reply-To: <20231025103957.3776-4-keith.zhao@starfivetech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 25/10/2023 13:39, Keith Zhao wrote: > For each modifier, add the corresponding description > > Signed-off-by: Keith Zhao > --- > include/uapi/drm/drm_fourcc.h | 57 +++++++++++++++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index 8db7fd3f7..a580a848c 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -419,6 +419,7 @@ extern "C" { > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a > +#define DRM_FORMAT_MOD_VENDOR_VERISILICON 0x0b > > /* add more to the end as needed */ > > @@ -1562,6 +1563,62 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > #define AMD_FMT_MOD_CLEAR(field) \ > (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) > > +#define DRM_FORMAT_MOD_VERISILICON_TYPE_NORMAL 0x00 > +#define DRM_FORMAT_MOD_VERISILICON_TYPE_MASK ((__u64)0x3 << 54) > + > +#define fourcc_mod_vs_code(type, val) \ > + fourcc_mod_code(VERISILICON, ((((__u64)type) << 54) | (val))) Please use fourcc_mode_code directly. > + > +#define DRM_FORMAT_MOD_VERISILICON_NORM_MODE_MASK 0x1F > + > +/* > + * An x-major 8x8 super tile consists of 64 8x8 sub-tiles in total. > + * Each 8x8 sub-tile consists of four standard tiles . > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_SUPER_TILED_XMAJOR_8X8 0x02 > + > +/* > + * A y-major 8x8 super tile consists of 64 8x8 sub-tiles in total. > + * Each 8x8 sub-tile consists of four standard tiles . > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_SUPER_TILED_YMAJOR_8X8 0x03 > + > +/* > + * An 8x8 tile consists of four standard tiles > + * that are organized in Z-order. > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_TILE_8X8 0x04 > + > +/* > + * An 8x4 tile consists of two standard tiles > + * that are organized in Z-order. > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_TILE_8X4 0x07 > + > +/* > + * An x-major 8x4 super tile consists of 128 8x4 sub-tiles in total. > + * Each 8x4 sub-tile consists of two standard tiles. > + * two standard tiles also same with DRM_FORMAT_MOD_VS_TILE_8X4 > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_SUPER_TILED_XMAJOR_8X4 0x0B > + > +/* > + * A y-major 4x8 super tile consists of 128 4x8 sub-tiles in total. > + * Each 4x8 sub-tile consists of two standard tiles. > + * two standard tiles also same with DRM_FORMAT_MOD_VS_TILE_8X4 > + * standard tiles (see Vivante 4x4 tiling layout) > + */ > +#define DRM_FORMAT_MOD_VERISILICON_SUPER_TILED_YMAJOR_4X8 0x0C > + > +#define fourcc_mod_vs_norm_code(tile) \ > + fourcc_mod_vs_code(DRM_FORMAT_MOD_VERISILICON_TYPE_NORMAL, \ > + (tile)) 1) this is not a part of uAPI 2) please use fourcc_mod_code directly. > + > #if defined(__cplusplus) > } > #endif -- With best wishes Dmitry