Re: [PATCH v2 0/2] irqchip/gic-v3: Enable non-coherent GIC designs probing

[Marc Zyngier <maz@kernel.org>]

On 2023-09-06 10:41, Lorenzo Pieralisi wrote:
> This series is v2 of a previous version[1].
> 
> v1 -> v2:
> 	- Updated DT bindings as per feedback
> 	- Updated patch[2] to use GIC quirks infrastructure
> 
> [1] 
> https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org
> 
> Original cover letter
> ---
> The GICv3 architecture specifications provide a means for the
> system programmer to set the shareability and cacheability
> attributes the GIC components (redistributors and ITSes) use
> to drive memory transactions.
> 
> Albeit the architecture give control over shareability/cacheability
> memory transactions attributes (and barriers), it is allowed to
> connect the GIC interconnect ports to non-coherent memory ports
> on the interconnect, basically tying off shareability/cacheability
> "wires" and de-facto making the redistributors and ITSes non-coherent
> memory observers.
> 
> This series aims at starting a discussion over a possible solution
> to this problem, by adding to the GIC device tree bindings the
> standard dma-noncoherent property. The GIC driver uses the property
> to force the redistributors and ITSes shareability attributes to
> non-shareable, which consequently forces the driver to use CMOs
> on GIC memory tables.
> 
> On ARM DT DMA is default non-coherent, so the GIC driver can't rely
> on the generic DT dma-coherent/non-coherent property management layer
> (of_dma_is_coherent()) which would default all GIC designs in the field
> as non-coherent; it has to rely on ad-hoc dma-noncoherent property 
> handling.
> 
> When a consistent approach is agreed upon for DT an equivalent binding 
> will
> be put forward for ACPI based systems.

What is the plan for this last point? I'd like to see at least
a proposal before taking this series in.

         M.
-- 
Jazz is not dead. It just smells funny...