From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Yang Xiwen <forbidden405@outlook.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v2 1/5] dt-bindings: clock: histb-clock: Add missing common clock and Hi3798MV200 specific clock definition
Date: Tue, 20 Feb 2024 11:16:44 +0100 [thread overview]
Message-ID: <6fa7119e-bbde-46a4-b556-2845ee2fad5b@linaro.org> (raw)
In-Reply-To: <SEZPR06MB6959939E06B2F6068094DC3A96502@SEZPR06MB6959.apcprd06.prod.outlook.com>
On 20/02/2024 11:12, Yang Xiwen wrote:
> On 2/20/2024 6:10 PM, Krzysztof Kozlowski wrote:
>> On 17/02/2024 13:52, Yang Xiwen via B4 Relay wrote:
>>> From: Yang Xiwen <forbidden405@outlook.com>
>>>
>>> According to the datasheet, some clocks are missing, add their
>>> definitions first.
>>>
>>> Some aliases for hi3798mv200 are also introduced.
>>>
>>> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
>>> ---
>>> include/dt-bindings/clock/histb-clock.h | 21 +++++++++++++++++++++
>>> 1 file changed, 21 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
>>> index e64e5770ada6..68a53053586a 100644
>>> --- a/include/dt-bindings/clock/histb-clock.h
>>> +++ b/include/dt-bindings/clock/histb-clock.h
>>> @@ -58,6 +58,27 @@
>>> #define HISTB_USB3_UTMI_CLK1 48
>>> #define HISTB_USB3_PIPE_CLK1 49
>>> #define HISTB_USB3_SUSPEND_CLK1 50
>>> +#define HISTB_SDIO1_BIU_CLK 51
>>> +#define HISTB_SDIO1_CIU_CLK 52
>>> +#define HISTB_SDIO1_DRV_CLK 53
>>> +#define HISTB_SDIO1_SAMPLE_CLK 54
>>> +#define HISTB_ETH0_PHY_CLK 55
>>> +#define HISTB_ETH1_PHY_CLK 56
>>> +#define HISTB_WDG0_CLK 57
>>> +#define HISTB_USB2_UTMI0_CLK HISTB_USB2_UTMI_CLK
>> Why? It's anyway placed oddly, the entries are ordered by number/value.
>>
>>> +#define HISTB_USB2_UTMI1_CLK 58
>>> +#define HISTB_USB3_REF_CLK 59
>>> +#define HISTB_USB3_GM_CLK 60
>>> +#define HISTB_USB3_GS_CLK 61
>>> +
>>> +/* Hi3798MV200 specific clocks */
>>> +
>>> +// reuse clocks of histb
>> Don't mix comment styles.
>>
>>> +#define HI3798MV200_GMAC_CLK HISTB_ETH0_MAC_CLK
>>> +#define HI3798MV200_GMACIF_CLK HISTB_ETH0_MACIF_CLK
>>> +#define HI3798MV200_FEMAC_CLK HISTB_ETH1_MAC_CLK
>>> +#define HI3798MV200_FEMACIF_CLK HISTB_ETH1_MACIF_CLK
>>> +#define HI3798MV200_FEPHY_CLK HISTB_ETH1_PHY_CLK
>> I don't understand what do you want to achieve here. Clock IDs start
>> from 0 or 1.
> They are aliases. A friendlier name compared to ETH0/1.
Fix your email client, so it will not remove line breaks before/after
quotes. Your email client makes it unreadable.
Aliases do not bind anything, so you can drop these.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-02-20 10:16 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-17 12:52 [PATCH RFC v2 0/5] clk: hisilicon: add support for Hi3798MV200 Yang Xiwen via B4 Relay
2024-02-17 12:52 ` [PATCH RFC v2 1/5] dt-bindings: clock: histb-clock: Add missing common clock and Hi3798MV200 specific clock definition Yang Xiwen via B4 Relay
2024-02-20 10:10 ` Krzysztof Kozlowski
2024-02-20 10:12 ` Yang Xiwen
2024-02-20 10:16 ` Krzysztof Kozlowski [this message]
2024-02-20 14:06 ` Yang Xiwen
2024-02-20 16:13 ` Krzysztof Kozlowski
2024-02-20 16:19 ` Yang Xiwen
2024-02-20 16:25 ` Krzysztof Kozlowski
2024-02-20 16:31 ` Yang Xiwen
2024-02-20 17:06 ` Krzysztof Kozlowski
2024-02-20 17:29 ` Yang Xiwen
2024-02-21 7:27 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 2/5] clk: hisilicon: add CRG driver for Hi3798MV200 SoC Yang Xiwen via B4 Relay
2024-02-20 10:11 ` Krzysztof Kozlowski
2024-02-20 10:14 ` Yang Xiwen
2024-02-20 10:17 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 3/5] dt-bindings: clock: merge all hisilicon clock bindings to hisilicon,clock-reset-generator Yang Xiwen via B4 Relay
2024-02-20 10:14 ` Krzysztof Kozlowski
2024-02-20 10:52 ` Yang Xiwen
2024-02-20 10:59 ` Krzysztof Kozlowski
2024-02-17 12:52 ` [PATCH RFC v2 4/5] dt-bindings: mfd: syscon: Add hisilicon,sdmmc-sap-dll compatible Yang Xiwen via B4 Relay
2024-02-17 12:52 ` [PATCH RFC v2 5/5] dt-bindings: clock: hisilicon,clock-reset-controller: add Hi3798MV200 SoC support Yang Xiwen via B4 Relay
2024-02-20 10:15 ` Krzysztof Kozlowski
2024-02-20 10:16 ` Yang Xiwen
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