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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa625e4dc95sm115378266b.38.2024.12.05.08.55.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 08:55:30 -0800 (PST) Message-ID: <6fe09de4-c94c-495d-92a4-aa902d2519ef@oss.qualcomm.com> Date: Thu, 5 Dec 2024 17:55:27 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] arm64: dts: qcom: ipq5332: Add PCIe related nodes To: Varadarajan Narayanan , lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, p.zabel@pengutronix.de, quic_nsekar@quicinc.com, dmitry.baryshkov@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: Praveenkumar I References: <20241204113329.3195627-1-quic_varada@quicinc.com> <20241204113329.3195627-6-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241204113329.3195627-6-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: -s5f8dgc0CZEVq4Xy9CzbbQUYrRi8voo X-Proofpoint-GUID: -s5f8dgc0CZEVq4Xy9CzbbQUYrRi8voo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050123 On 4.12.2024 12:33 PM, Varadarajan Narayanan wrote: > From: Praveenkumar I > > Add phy and controller nodes for pcie0_x1 and pcie1_x2. > > Signed-off-by: Praveenkumar I > Signed-off-by: Varadarajan Narayanan > --- [...] > + pcie0: pcie@20000000 { > + compatible = "qcom,pcie-ipq5332"; > + reg = <0x20000000 0xf1d>, > + <0x20000F20 0xa8>, Please use lowercase hex > + <0x20001000 0x1000>, > + <0x00080000 0x3000>, > + <0x20100000 0x1000>; > + reg-names = "dbi", "elbi", "atu", "parf", "config"; Please also add the MHI region > + device_type = "pci"; > + linux,pci-domain = <0>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */ > + <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */ Please drop these comments > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ And these too > + > + clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, > + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, > + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, > + <&gcc GCC_PCIE3X1_0_RCHG_CLK>, > + <&gcc GCC_PCIE3X1_0_AHB_CLK>, > + <&gcc GCC_PCIE3X1_0_AUX_CLK>; > + Stray newline > + clock-names = "axi_m", > + "axi_s", > + "axi_bridge", > + "rchng", > + "ahb", > + "aux"; > + > + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, > + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, > + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, > + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, > + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, > + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>, > + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>; > + Ditto > + reset-names = "pipe", > + "sticky", > + "axi_s_sticky", > + "axi_s", > + "axi_m_sticky", > + "axi_m", > + "aux", > + "ahb"; > + > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + > + interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, > + <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + > + msi-map = <0x0 &v2m0 0x0 0xffd>; > + status = "disabled"; > + }; > + > + pcie1: pcie@18000000 { Same comments as pcie0 Konrad