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Fri, 29 Nov 2024 02:20:46 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AT2KkFp032347 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Nov 2024 02:20:46 GMT Received: from [10.233.21.53] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 28 Nov 2024 18:20:42 -0800 Message-ID: <7083653c-15c6-4971-b9ca-cd7fa02a9a75@quicinc.com> Date: Fri, 29 Nov 2024 10:20:40 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , , , , , , Krzysztof Kozlowski References: <20241128-qcs8300_initial_dtsi-v3-0-26aa8a164914@quicinc.com> <20241128-qcs8300_initial_dtsi-v3-2-26aa8a164914@quicinc.com> Content-Language: en-US From: Jingyi Wang In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7FY4LVx6QF9Uqp1KKhJ7dnSWgNtxdbXv X-Proofpoint-ORIG-GUID: 7FY4LVx6QF9Uqp1KKhJ7dnSWgNtxdbXv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=828 priorityscore=1501 clxscore=1015 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411290017 On 11/28/2024 9:12 PM, Dmitry Baryshkov wrote: > On Thu, Nov 28, 2024 at 04:44:44PM +0800, Jingyi Wang wrote: >> Enable clock controller, interconnect and pinctrl for Qualcomm >> QCS8300 platform to boot to UART console. > > ... which is used on the ABC DEF board. The defconfig is being enabled > for everybody, so at least let them know which board increases the size > of the default kernel build. > will add that >> >> The serial engine depends on gcc, interconnect and pinctrl. Since >> the serial console driver is only available as built-in, so these >> configs needs be built-in for the UART device to probe and register >> the console. >> >> Reviewed-by: Krzysztof Kozlowski >> Signed-off-by: Jingyi Wang >> --- >> arch/arm64/configs/defconfig | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index d13218d0c30f..3d9e48940c96 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -608,6 +608,7 @@ CONFIG_PINCTRL_MSM8996=y >> CONFIG_PINCTRL_MSM8998=y >> CONFIG_PINCTRL_QCM2290=y >> CONFIG_PINCTRL_QCS404=y >> +CONFIG_PINCTRL_QCS8300=y >> CONFIG_PINCTRL_QDF2XXX=y >> CONFIG_PINCTRL_QDU1000=y >> CONFIG_PINCTRL_SA8775P=y >> @@ -1327,6 +1328,7 @@ CONFIG_MSM_MMCC_8998=m >> CONFIG_QCM_GCC_2290=y >> CONFIG_QCM_DISPCC_2290=m >> CONFIG_QCS_GCC_404=y >> +CONFIG_QCS_GCC_8300=y >> CONFIG_SC_CAMCC_7280=m >> CONFIG_QDU_GCC_1000=y >> CONFIG_SC_CAMCC_8280XP=m >> @@ -1634,6 +1636,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >> CONFIG_INTERCONNECT_QCOM_QCM2290=y >> CONFIG_INTERCONNECT_QCOM_QCS404=m >> +CONFIG_INTERCONNECT_QCOM_QCS8300=y >> CONFIG_INTERCONNECT_QCOM_QDU1000=y >> CONFIG_INTERCONNECT_QCOM_SA8775P=y >> CONFIG_INTERCONNECT_QCOM_SC7180=y >> >> -- >> 2.25.1 >> > Thanks, Jingyi