From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 737A8C7EE23 for ; Thu, 8 Jun 2023 12:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236288AbjFHMnJ (ORCPT ); Thu, 8 Jun 2023 08:43:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232898AbjFHMnI (ORCPT ); Thu, 8 Jun 2023 08:43:08 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C26926B1; Thu, 8 Jun 2023 05:43:07 -0700 (PDT) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3589A91B001978; Thu, 8 Jun 2023 14:42:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=73FqTMHLfZiM2PDdNj01tEfDAdrx6SjM7RVnmCFe2B8=; b=4U+Z3T3jg8g0fU7KYtC97DzZXEbG/CAEbEU6Ff39w/KzY01TVklN0VgZfSesjS6ImUIE cR9q12YfpIQ/ZO+prvC0PTY57NcV+wQL5vAJdmDN6ZfQbLYv6VusPCHP1vRz3VKuCoPW LZ9wEDDOJ3d1Bp6aj9qQT/qJXk43jqh5jZrY8CmR/uBCBRn/nMXMtdNNlVc54fG3i/HP ndfZz0jJXQor7SWg28LhXAh8AJX1oVO3aoF9JGnqGz5K6x9v+gWmkZFy6K/M9HWO119R BVypJk1UkpS6nTOl1e/w4c9QEhg8EMIYBx4mF5s1KivCcRLWtbeFvmANioXVkdW32qJ4 5g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3r3c4ahc5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Jun 2023 14:42:50 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1458610003D; Thu, 8 Jun 2023 14:42:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 06624209BA9; Thu, 8 Jun 2023 14:42:44 +0200 (CEST) Received: from [10.201.21.93] (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 8 Jun 2023 14:42:43 +0200 Message-ID: <7139fb21-6a1d-a26f-fef3-d3154d234ca2@foss.st.com> Date: Thu, 8 Jun 2023 14:42:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [RESEND PATCH v2 2/6] ARM: dts: stm32: add pin map for LTDC on stm32f7 Content-Language: en-US To: Dario Binacchi , CC: Raphael Gallais-Pou , , , Philippe Cornu , Amarula patchwork , Maxime Coquelin , , , Conor Dooley , Krzysztof Kozlowski , Rob Herring , References: <20230607063139.621351-1-dario.binacchi@amarulasolutions.com> <20230607063139.621351-3-dario.binacchi@amarulasolutions.com> From: Alexandre TORGUE In-Reply-To: <20230607063139.621351-3-dario.binacchi@amarulasolutions.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-08_09,2023-06-08_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Dario On 6/7/23 08:31, Dario Binacchi wrote: > Add pin configurations for using LTDC (LCD-tft Display Controller) on > stm32f746-disco board. > > Signed-off-by: Dario Binacchi > --- > > (no changes since v1) > > arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 35 ++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi > index 9f65403295ca..f3f90b9bcd61 100644 > --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi > @@ -365,6 +365,41 @@ pins2 { > bias-pull-up; > }; > }; > + > + > + ltdc_pins_a: ltdc-pins-a-0 { ltdc-pins-a-0 --> ltdc-pins-0 is a bit cleaner. I know that I have to fix sdio pins nodes in this file to keep the same spirit for all group names. If there is no V3 I wil do it directly when I'll apply DT patches if you agree. Alex > + pins { > + pinmux = , /* LCD_B0 */ > + , /* LCD_B4 */ > + , /* LCD_VSYNC */ > + , /* LCD_HSYNC */ > + , /* LCD_CLK */ > + , /* LCD_R0 */ > + , /* LCD_R1 */ > + , /* LCD_R2 */ > + , /* LCD_R3 */ > + , /* LCD_R4 */ > + , /* LCD_R5 */ > + , /* LCD_R6 */ > + , /* LCD_R7 */ > + , /* LCD_G0 */ > + , /* LCD_G1 */ > + , /* LCD_G2 */ > + , /* LCD_G3 */ > + , /* LCD_G4 */ > + , /* LCD_B1 */ > + , /* LCD_B2 */ > + , /* LCD_B3 */ > + , /* LCD_G5 */ > + , /* LCD_G6 */ > + , /* LCD_G7 */ > + , /* LCD_B5 */ > + , /* LCD_B6 */ > + , /* LCD_B7 */ > + ; /* LCD_DE */ > + slew-rate = <2>; > + }; > + }; > }; > }; > };