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([2a01:e0a:3d9:2080:4144:6a84:fe1d:3aae]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532063ebf6sm56506385e9.3.2025.06.13.02.18.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jun 2025 02:18:18 -0700 (PDT) Message-ID: <7178e816-4cb4-49b3-9a1e-1ecd4caa43ed@linaro.org> Date: Fri, 13 Jun 2025 11:18:17 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH 0/7] Add ASPEED PCIe Root Complex support To: Jacky Chou , bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, vkoul@kernel.org, kishon@kernel.org, linus.walleij@linaro.org, p.zabel@pengutronix.de, linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org Cc: elbadrym@google.com, romlem@google.com, anhphan@google.com, wak@google.com, yuxiaozhang@google.com, BMC-SW@aspeedtech.com References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 13/06/2025 05:29, Jacky Chou wrote: > This patch series adds support for the ASPEED PCIe Root Complex, > including device tree bindings, pinctrl support, and the PCIe host controller > driver. The patches introduce the necessary device tree nodes, pinmux groups, > and driver implementation to enable PCIe functionality on ASPEED platforms. > > Summary of changes: > - Add device tree binding documents for ASPEED PCIe PHY, PCIe Config, and PCIe RC > - Update MAINTAINERS for new bindings and driver > - Add PCIe RC node and PERST control pin to aspeed-g6 device tree > - Add PCIe RC PERST pin group to aspeed-g6 pinctrl > - Implement ASPEED PCIe Root Complex host controller driver > > This series has been tested on AST2600/AST2700 platforms and enables PCIe device > enumeration and operation. > > Feedback and review are welcome. So it seems all PCIe RC code is bundled in a single driver and there's no PCIe PHY driver code, is there a reason for that ? If yes I think it should be described in the cover letter. Thanks, Neil > > Jacky Chou (7): > dt-bindings: phy: Add document for ASPEED PCIe PHY > dt-bindings: pci: Add document for ASPEED PCIe Config > dt-bindings: pci: Add document for ASPEED PCIe RC > ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin > ARM: dts: aspeed-g6: Add PCIe RC node > pinctrl: aspeed-g6: Add PCIe RC PERST pin group > pci: aspeed: Add ASPEED PCIe host controller driver > > .../bindings/pci/aspeed-pcie-cfg.yaml | 41 + > .../devicetree/bindings/pci/aspeed-pcie.yaml | 159 +++ > .../bindings/phy/aspeed-pcie-phy.yaml | 38 + > MAINTAINERS | 10 + > .../boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 + > arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 53 + > drivers/pci/controller/Kconfig | 13 + > drivers/pci/controller/Makefile | 1 + > drivers/pci/controller/pcie-aspeed.c | 1039 +++++++++++++++++ > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 12 +- > 10 files changed, 1370 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml > create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > create mode 100644 Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml > create mode 100644 drivers/pci/controller/pcie-aspeed.c >