[PATCH v3 1/4] dt-bindings: PCI: qcom: adjust iommu-map for different SoC

Krzysztof Kozlowski
2023-12-08T10:52:03Z

The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998
has one and SDM845 has sixteen, so allow wider number of items to fix
dtbs_check warnings like:

qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1],
[512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

Please take the patch via PCI tree.

Changes in v3:
1. None

Changes in v2:
1. Add Acs/Rb.
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 9dbc07dfd48f..5056da499f04 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -66,7 +66,8 @@ properties:
maxItems: 8

iommu-map:
- maxItems: 2
+ minItems: 1
+ maxItems: 16

# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
--
2.34.1