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AJvYcCWmINNYeL6e3GZZdHOj9r36/dZ/VWXyGsUcmIQzTzYlW6hRCt8zXrm28Q7QylFndCMxcUA5BGNWcA7KxzgPvM8l9BEG0qqdVGlarA== X-Gm-Message-State: AOJu0Yzn6yjHp4gdTTv1JTHN5MrZQFnDmMPZWKHLAxpbzx0th+BFHouE hkYu9Z4T/VrOGkmNMPgyg8NGMnuQZWWiofaiYKqS9yMjBdU6xD3yz2ZL8WjQbmk9inzZT8+AsqR F X-Google-Smtp-Source: AGHT+IFYjEWHXZNGVIdDOUHife0DwAl47pjuT11DGcHdgJFzG89QSi8SN5G0rSimAf7gcq/tXvbxJw== X-Received: by 2002:a0c:dd91:0:b0:68e:fcc4:cb22 with SMTP id v17-20020a0cdd91000000b0068efcc4cb22mr10908385qvk.35.1708270153536; Sun, 18 Feb 2024 07:29:13 -0800 (PST) Received: from [100.64.0.1] ([170.85.8.176]) by smtp.gmail.com with ESMTPSA id lq2-20020a0562145b8200b0068f4659b8d0sm1741150qvb.107.2024.02.18.07.29.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Feb 2024 07:29:13 -0800 (PST) Message-ID: <72221da1-4a1a-4947-a202-9de203032f5c@sifive.com> Date: Sun, 18 Feb 2024 09:29:11 -0600 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property Content-Language: en-US To: Krzysztof Kozlowski , Will Deacon , Mark Rutland , Eric Lin , Conor Dooley Cc: Palmer Dabbelt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org References: <20240216000837.1868917-1-samuel.holland@sifive.com> <20240216000837.1868917-2-samuel.holland@sifive.com> From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Krzysztof, On 2024-02-17 3:00 AM, Krzysztof Kozlowski wrote: > On 16/02/2024 01:08, Samuel Holland wrote: >> The SiFive Composable Cache controller contains an optional PMU with a >> configurable number of event counters. Document a property which > > Configurable in what context? By chip designers or by OS? Why this > cannot be deduced from the compatible? This parameter is configurable by the chip designers. The information certainly can be deduced from the SoC-specific compatible string, but doing so makes the driver only work on that specific list of SoCs. When provided via a property, the driver can work without changes on any SoC that uses this IP block. (None of the SoCs currently listed in the binding contain a PMU, so there is no backward compatibility concern with adding the new property.) My understanding of the purpose of the SoC-specific compatible string is to handle eventualities (silicon bugs, integration quirks, etc.), not to intentionally limit the driver to a narrow list of hardware. Regards, Samuel >> describes the number of available counters. >> >> Signed-off-by: Samuel Holland >> --- >> >> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >>