From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Murali Karicheri <m-karicheri2@ti.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Rob Herring <robh+dt@kernel.org>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Kumar Gala <galak@codeaurora.org>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] PCI: keystone: update to support multiple pci ports
Date: Fri, 05 Sep 2014 19:54:58 +0200 [thread overview]
Message-ID: <7260053.FoBVhTXVfj@wuerfel> (raw)
In-Reply-To: <1409938782-31460-1-git-send-email-m-karicheri2@ti.com>
On Friday 05 September 2014 13:39:42 Murali Karicheri wrote:
> +
> /* enable RC mode in devcfg */
> val = readl(reg_p);
> - val &= ~PCIE_MODE_MASK;
> - val |= PCIE_RC_MODE;
> + port_id <<= 1;
> + val &= ~(PCIE_MODE_MASK << port_id);
> + val |= (PCIE_RC_MODE << port_id);
> writel(val, reg_p);
> + devm_iounmap(dev, reg_p);
> + devm_release_mem_region(dev, res->start, resource_size(res));
This looks like it's a shared register of some sort that doesn't
really belong into the registers of a particular port. Could it
be that it's actually for the PHY?
Arnd
next prev parent reply other threads:[~2014-09-05 17:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-05 17:39 [PATCH] PCI: keystone: update to support multiple pci ports Murali Karicheri
2014-09-05 17:54 ` Arnd Bergmann [this message]
2014-09-05 18:33 ` Murali Karicheri
[not found] ` <540A0212.6060303-l0cyMroinI0@public.gmane.org>
2014-09-05 19:00 ` Arnd Bergmann
2014-09-05 20:37 ` Murali Karicheri
2014-09-05 21:11 ` Arnd Bergmann
2014-09-08 15:52 ` Murali Karicheri
2014-09-09 10:24 ` Arnd Bergmann
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