[PATCH 0/8] arm64: dts: Add Arm Morello support

[PATCH 0/8] arm64: dts: Add Arm Morello support

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA [1].

This series adds dts support for the Arm Morello System Development
Platform.

[1] https://www.morello-project.org/

To simplify the testing a linux tree rebased on 6.13-rc2 is accessible
at [2].

[2] https://codeberg.org/vincenzo/linux/src/branch/morello/dts/v1

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Vincenzo Frascino (8):
  dt-bindings: arm: Add Morello compatibility
  dt-bindings: mailbox: arm,mhu: Add missing properties
  arm64: dts: morello: Add support for common functionalities
  arm64: dts: morello: Add support for soc dts
  arm64: Introduce Arm Morello System Development Platform
  arm64: dts: Add Arm Morello System Development Platform support
  arm64: Enable Arm Morello System Development Platform support
  MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

 .../bindings/arm/arm,vexpress-juno.yaml       |   3 +
 .../devicetree/bindings/mailbox/arm,mhu.yaml  |  10 +
 MAINTAINERS                                   |   6 +
 arch/arm64/Kconfig.platforms                  |   5 +
 arch/arm64/boot/dts/arm/Makefile              |   1 +
 arch/arm64/boot/dts/arm/morello-soc.dts       | 267 ++++++++++++++++++
 arch/arm64/boot/dts/arm/morello.dtsi          | 112 ++++++++
 arch/arm64/configs/defconfig                  |   1 +
 8 files changed, 405 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts
 create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi

-- 
2.43.0

[PATCH 1/8] dt-bindings: arm: Add Morello compatibility

[Vincenzo Frascino]

Add compatibility to Arm Morello System Development Platform.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
index 8dd6b6446394..ea5a5e179ed1 100644
--- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
@@ -118,6 +118,9 @@ properties:
         items:
           - const: arm,foundation-aarch64
           - const: arm,vexpress
+      - description: Arm Morello System Development Platform
+        items:
+          - const: arm,morello
 
   arm,vexpress,position:
     description: When daughterboards are stacked on one site, their position
-- 
2.43.0

[PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties

[Vincenzo Frascino]

Add support for "interrupt-names" and "mbox-name" optional properties.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
index d9a4f4a02d7c..65a4f66a7273 100644
--- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
@@ -63,6 +63,16 @@ properties:
       - description: high-priority non-secure
       - description: Secure
 
+  interrupt-names:
+    minItems: 2
+    items:
+      - const: mhu-lpri-rx
+      - const: mhu-hpri-rx
+      - const: mhu-si-rx
+
+  mbox-name:
+    maxItems: 1
+
   clocks:
     maxItems: 1
 
-- 
2.43.0

[PATCH 3/8] arm64: dts: morello: Add support for common functionalities

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
some functionalities that have conveniently been included in
morello.dtsi to avoid duplication.

Introduce morello.dtsi.

Note: Morello fvp will be introduced with a future patch series.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/morello.dtsi | 112 +++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi

diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
new file mode 100644
index 000000000000..9d84a0840c5b
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "arm,morello";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &soc_uart0;
+	};
+
+	gic: interrupt-controller@2c010000 {
+		compatible = "arm,gic-v3";
+		#address-cells = <2>;
+		#interrupt-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	spe-pmu {
+		compatible = "arm,statistical-profiling-extension-v1";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	mailbox: mhu@45000000 {
+		compatible = "arm,mhu-doorbell", "arm,primecell";
+		reg = <0x0 0x45000000 0x0 0x1000>;
+		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mhu-lpri-rx",
+				  "mhu-hpri-rx";
+		#mbox-cells = <2>;
+		mbox-name = "ARM-MHU";
+		clocks = <&soc_refclk50mhz>;
+		clock-names = "apb_pclk";
+	};
+
+	sram: sram@45200000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x06000000 0x0 0x8000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0x06000000 0x8000>;
+
+		cpu_scp_hpri0: scp-sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x80>;
+		};
+
+		cpu_scp_hpri1: scp-sram@80 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x80 0x80>;
+		};
+	};
+
+	soc_refclk50mhz: refclk50mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "apb_pclk";
+	};
+
+	soc_refclk85mhz: refclk85mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <85000000>;
+		clock-output-names = "iofpga:aclk";
+	};
+
+	soc_uartclk:  uartclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "uartclk";
+	};
+
+	soc_uart0: serial@2a400000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x2a400000 0x0 0x1000>;
+		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
-- 
2.43.0

[PATCH 4/8] arm64: dts: morello: Add support for soc dts

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

Introduce Morello SoC dts.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++
 1 file changed, 267 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts

diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts
new file mode 100644
index 000000000000..3c5247121e4d
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-soc.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+	model = "Arm Morello System Development Platform";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure-firmware@ff000000 {
+			reg = <0 0xff000000 0 0x01000000>;
+			no-map;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cpu0: cpu0@0 {
+			compatible = "arm,neoverse-n1";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+		cpu1: cpu1@100 {
+			compatible = "arm,neoverse-n1";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+		cpu2: cpu2@10000 {
+			compatible = "arm,neoverse-n1";
+			reg = <0x0 0x10000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 1>;
+		};
+		cpu3: cpu3@10100 {
+			compatible = "arm,neoverse-n1";
+			reg = <0x0 0x10100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 1>;
+		};
+	};
+
+	/* The first bank of memory, memory map is actually provided by UEFI. */
+	memory@80000000 {
+		device_type = "memory";
+		/* [0x80000000-0xffffffff] */
+		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
+	};
+
+	memory@8080000000 {
+		device_type = "memory";
+		/* [0x8080000000-0x83f7ffffff] */
+		reg = <0x00000080 0x80000000 0x3 0x78000000>;
+	};
+
+	smmu_pcie: iommu@4f400000 {
+		compatible = "arm,smmu-v3";
+		reg = <0 0x4f400000 0 0x40000>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		msi-parent = <&its2 0>;
+		#iommu-cells = <1>;
+		dma-coherent;
+	};
+
+	pcie_ctlr: pcie@28c0000000 {
+		compatible = "pci-host-ecam-generic";
+		device_type = "pci";
+		reg = <0x28 0xC0000000 0 0x10000000>;
+		bus-range = <0 255>;
+		linux,pci-domain = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		dma-coherent;
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
+		     <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
+			 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
+		msi-map = <0 &its_pcie 0 0x10000>;
+		iommu-map = <0 &smmu_pcie 0 0x10000>;
+		status = "okay";
+	};
+
+	smmu_ccix: iommu@4f000000 {
+		compatible = "arm,smmu-v3";
+		reg = <0 0x4f000000 0 0x40000>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		msi-parent = <&its1 0>;
+		#iommu-cells = <1>;
+		dma-coherent;
+	};
+
+	ccix_pcie_ctlr: pcie@4fc0000000 {
+		compatible = "pci-host-ecam-generic";
+		device_type = "pci";
+		reg = <0x4F 0xC0000000 0 0x10000000>;
+		bus-range = <0 255>;
+		linux,pci-domain = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		dma-coherent;
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
+		     <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
+			 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
+		msi-map = <0 &its_ccix 0 0x10000>;
+		iommu-map = <0 &smmu_ccix 0 0x10000>;
+		status = "okay";
+	};
+
+	smmu_dp: iommu@2ce00000 {
+		compatible = "arm,smmu-v3";
+		reg = <0 0x2ce00000 0 0x40000>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "gerror", "cmdq-sync";
+		#iommu-cells = <1>;
+	};
+
+	dp0: display@2cc00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "arm,mali-d32", "arm,mali-d71";
+		reg = <0 0x2cc00000 0 0x20000>;
+		interrupts = <0 69 4>;
+		clocks = <&dpu_aclk>;
+		clock-names = "aclk";
+		iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
+			<&smmu_dp 8>;
+
+		pl0: pipeline@0 {
+			reg = <0>;
+			clocks = <&dpu_pixel_clk>;
+			clock-names = "pxclk";
+			port {
+				dp_pl0_out0: endpoint {
+					remote-endpoint = <&tda998x_0_input>;
+				};
+			};
+		};
+	};
+
+	i2c@1c0f0000 {
+		compatible = "cdns,i2c-r1p14";
+		reg = <0x0 0x1c0f0000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <100000>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&dpu_aclk>;
+
+		hdmi_tx: hdmi-transmitter@70 {
+			compatible = "nxp,tda998x";
+			reg = <0x70>;
+			video-ports = <0x234501>;
+			port {
+				tda998x_0_input: endpoint {
+					remote-endpoint = <&dp_pl0_out0>;
+				};
+			};
+		};
+	};
+
+	dpu_aclk: dpu_aclk {
+		/* 77.1 MHz derived from 24 MHz reference clock */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <350000000>;
+		clock-output-names = "aclk";
+	};
+
+	dpu_pixel_clk: dpu-pixel-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+		clock-output-names = "pxclk";
+	};
+
+	firmware {
+		scmi {
+			compatible = "arm,scmi";
+			mbox-names = "tx", "rx";
+			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
+			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			scmi_dvfs: protocol@13 {
+				reg = <0x13>;
+				#clock-cells = <1>;
+			};
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+};
+
+&gic {
+	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
+	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
+	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+	its1: msi-controller@30040000 {
+		compatible = "arm,gic-v3-its";
+		msi-controller;
+		#msi-cells = <1>;
+		reg = <0x0 0x30040000 0x0 0x20000>;
+	};
+
+	its2: msi-controller@30060000 {
+		compatible = "arm,gic-v3-its";
+		msi-controller;
+		#msi-cells = <1>;
+		reg = <0x0 0x30060000 0x0 0x20000>;
+	};
+
+	its_ccix: msi-controller@30080000 {
+		compatible = "arm,gic-v3-its";
+		msi-controller;
+		#msi-cells = <1>;
+		reg = <0x0 0x30080000 0x0 0x20000>;
+	};
+
+	its_pcie: msi-controller@300a0000 {
+		compatible = "arm,gic-v3-its";
+		msi-controller;
+		#msi-cells = <1>;
+		reg = <0x0 0x300a0000 0x0 0x20000>;
+	};
+};
-- 
2.43.0

[PATCH 5/8] arm64: Introduce Arm Morello System Development Platform

[Vincenzo Frascino]

Introduce the Kconfig entry for the Arm Morello System Development
Platform.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 370a9d2b6919..1c4867ea9407 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -250,6 +250,11 @@ config ARCH_NPCM
 	  General support for NPCM8xx BMC (Arbel).
 	  Nuvoton NPCM8xx BMC based on the Cortex A35.
 
+config ARCH_MORELLO
+	bool "Arm Morello System Development Platform"
+	help
+	  Enables support for Arm Morello System Development Platform
+
 config ARCH_PENSANDO
 	bool "AMD Pensando Platforms"
 	help
-- 
2.43.0

[PATCH 6/8] arm64: dts: Add Arm Morello System Development Platform support

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

Introduce Arm Morello System Development Platform support.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index d908e96d7ddc..0a821808692e 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
+dtb-$(CONFIG_ARCH_MORELLO) += morello-soc.dtb
-- 
2.43.0

[PATCH 7/8] arm64: Enable Arm Morello System Development Platform support

[Vincenzo Frascino]

Enable Arm Morello System Development Platform support in defconfig.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c62831e61586..44b97b0b1e62 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -58,6 +58,7 @@ CONFIG_ARCH_LAYERSCAPE=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_S32=y
 CONFIG_ARCH_MA35=y
+CONFIG_ARCH_MORELLO=y
 CONFIG_ARCH_NPCM=y
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_REALTEK=y
-- 
2.43.0

[PATCH 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Vincenzo Frascino]

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e6e71b05710b..8199e5945fb2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3304,6 +3304,12 @@ F:	drivers/clocksource/timer-versatile.c
 X:	drivers/cpufreq/vexpress-spc-cpufreq.c
 X:	Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
 
+ARM MORELLO PLATFORM SUPPORT
+M:	Vincenzo Frascino <vincenzo.frascino@arm.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm64/boot/dts/arm/morello*
+
 ARM/VFP SUPPORT
 M:	Russell King <linux@armlinux.org.uk>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.43.0

Re: [PATCH 1/8] dt-bindings: arm: Add Morello compatibility

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> Add compatibility to Arm Morello System Development Platform.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
> index 8dd6b6446394..ea5a5e179ed1 100644
> --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
> +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
> @@ -118,6 +118,9 @@ properties:
>          items:
>            - const: arm,foundation-aarch64
>            - const: arm,vexpress
> +      - description: Arm Morello System Development Platform
> +        items:
> +          - const: arm,morello

Why is this only SoC? Your commit msg is supposed to explain any
oddities, because on first look that's just clearly wrong.

Best regards,
Krzysztof

Re: [PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> Add support for "interrupt-names" and "mbox-name" optional properties.

Why?


I wonder why you are not cc-ing other maintainers, like only Rob is
acceptable by you?

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument, so you will
not CC people just because they made one commit years ago). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.
</form letter>

> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
> index d9a4f4a02d7c..65a4f66a7273 100644
> --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
> @@ -63,6 +63,16 @@ properties:
>        - description: high-priority non-secure
>        - description: Secure
>  
> +  interrupt-names:
> +    minItems: 2
> +    items:
> +      - const: mhu-lpri-rx
> +      - const: mhu-hpri-rx
> +      - const: mhu-si-rx

No, drop.

> +
> +  mbox-name:
> +    maxItems: 1

No clue what's this, for sure there is no such property at all and
commit msg does not explain it.


Drop entire patch.

Best regards,
Krzysztof

Re: [PATCH 3/8] arm64: dts: morello: Add support for common functionalities

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
> 
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
> 
> Introduce morello.dtsi.
> 
> Note: Morello fvp will be introduced with a future patch series.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  arch/arm64/boot/dts/arm/morello.dtsi | 112 +++++++++++++++++++++++++++
>  1 file changed, 112 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
> 
> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
> new file mode 100644
> index 000000000000..9d84a0840c5b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/morello.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "arm,morello";
> +
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &soc_uart0;
> +	};
> +
> +	gic: interrupt-controller@2c010000 {
> +		compatible = "arm,gic-v3";
> +		#address-cells = <2>;
> +		#interrupt-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		interrupt-controller;
> +	};
> +
> +	pmu {
> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	spe-pmu {
> +		compatible = "arm,statistical-profiling-extension-v1";
> +		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	mailbox: mhu@45000000 {


You cannot have MMIO nodes outside of soc.

> +		compatible = "arm,mhu-doorbell", "arm,primecell";
> +		reg = <0x0 0x45000000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "mhu-lpri-rx",
> +				  "mhu-hpri-rx";
> +		#mbox-cells = <2>;
> +		mbox-name = "ARM-MHU";
> +		clocks = <&soc_refclk50mhz>;
> +		clock-names = "apb_pclk";
> +	};
> +
> +	sram: sram@45200000 {
> +		compatible = "mmio-sram";
> +		reg = <0x0 0x06000000 0x0 0x8000>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x0 0x06000000 0x8000>;
> +
> +		cpu_scp_hpri0: scp-sram@0 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x80>;
> +		};
> +
> +		cpu_scp_hpri1: scp-sram@80 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x80 0x80>;
> +		};
> +	};
> +
> +	soc_refclk50mhz: refclk50mhz {

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;
> +		clock-output-names = "apb_pclk";
> +	};
> +
> +	soc_refclk85mhz: refclk85mhz {

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1


> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <85000000>;
> +		clock-output-names = "iofpga:aclk";
> +	};
> +
> +	soc_uartclk:  uartclk {


Only one space.

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;
> +		clock-output-names = "uartclk";
> +	};
> +
> +	soc_uart0: serial@2a400000 {
> +		compatible = "arm,pl011", "arm,primecell";
> +		reg = <0x0 0x2a400000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
> +		clock-names = "uartclk", "apb_pclk";
> +		status = "okay";

Why do you need it? Did you disable it?

> +	};
> +};


Best regards,
Krzysztof

Re: [PATCH 4/8] arm64: dts: morello: Add support for soc dts

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
> 
> Introduce Morello SoC dts.

So Morello is an architecture, not a board or platform? You cannot have
both...




> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++
>  1 file changed, 267 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts
> 
> diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts
> new file mode 100644
> index 000000000000..3c5247121e4d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/morello-soc.dts
> @@ -0,0 +1,267 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
> +
> + */
> +
> +/dts-v1/;
> +#include "morello.dtsi"
> +
> +/ {
> +	model = "Arm Morello System Development Platform";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		secure-firmware@ff000000 {
> +			reg = <0 0xff000000 0 0x01000000>;
> +			no-map;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +		cpu0: cpu0@0 {
> +			compatible = "arm,neoverse-n1";
> +			reg = <0x0 0x0>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +		cpu1: cpu1@100 {
> +			compatible = "arm,neoverse-n1";
> +			reg = <0x0 0x100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +		cpu2: cpu2@10000 {
> +			compatible = "arm,neoverse-n1";
> +			reg = <0x0 0x10000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 1>;
> +		};
> +		cpu3: cpu3@10100 {
> +			compatible = "arm,neoverse-n1";
> +			reg = <0x0 0x10100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 1>;
> +		};
> +	};
> +
> +	/* The first bank of memory, memory map is actually provided by UEFI. */
> +	memory@80000000 {
> +		device_type = "memory";
> +		/* [0x80000000-0xffffffff] */
> +		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
> +	};
> +
> +	memory@8080000000 {
> +		device_type = "memory";
> +		/* [0x8080000000-0x83f7ffffff] */
> +		reg = <0x00000080 0x80000000 0x3 0x78000000>;
> +	};
> +
> +	smmu_pcie: iommu@4f400000 {

This all is weird. MMIO nodes outside of soc, soc pieces defined in DTS
instead of DTSI.

Please look first how all other DTS and DTSI are done. Also carefully
read DTS coding style.



Best regards,
Krzysztof

Re: [PATCH 5/8] arm64: Introduce Arm Morello System Development Platform

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> Introduce the Kconfig entry for the Arm Morello System Development
> Platform.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  arch/arm64/Kconfig.platforms | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 370a9d2b6919..1c4867ea9407 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -250,6 +250,11 @@ config ARCH_NPCM
>  	  General support for NPCM8xx BMC (Arbel).
>  	  Nuvoton NPCM8xx BMC based on the Cortex A35.
>  
> +config ARCH_MORELLO
> +	bool "Arm Morello System Development Platform"
> +	help
> +	  Enables support for Arm Morello System Development Platform

You do not get new ARCH per each soc or product. Merge it to existing
ARM Kconfigs.

Best regards,
Krzysztof

Re: [PATCH 6/8] arm64: dts: Add Arm Morello System Development Platform support

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
> 
> Introduce Arm Morello System Development Platform support.
> 
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  arch/arm64/boot/dts/arm/Makefile | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
> index d908e96d7ddc..0a821808692e 100644
> --- a/arch/arm64/boot/dts/arm/Makefile
> +++ b/arch/arm64/boot/dts/arm/Makefile
> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
>  dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
>  dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
>  dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
> +dtb-$(CONFIG_ARCH_MORELLO) += morello-soc.dtb

No, you organize patches in insane way. Makefile is never, never
separate entry.

Look how all existing submissions were done.

Squash the patches.

You also did not CC several people and at least arm kernel list. Use
standard tools for development instead of inventing your own process.

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument, so you will
not CC people just because they made one commit years ago). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.
</form letter>



Best regards,
Krzysztof

Re: [PATCH 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Krzysztof Kozlowski]

On 13/12/2024 17:32, Vincenzo Frascino wrote:
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  MAINTAINERS | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e6e71b05710b..8199e5945fb2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3304,6 +3304,12 @@ F:	drivers/clocksource/timer-versatile.c
>  X:	drivers/cpufreq/vexpress-spc-cpufreq.c
>  X:	Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>  
> +ARM MORELLO PLATFORM SUPPORT

Wrongly placed, M is not after V, I know people cannot keep order but
let's try. No need for new Boogaloo.

Plus look how all the titles are created and do not come with different
style.

> +M:	Vincenzo Frascino <vincenzo.frascino@arm.com>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)


So why you did not bother to Cc this list? You are supposed to develop
on mainline kernel and then run get_maintainers.pl or b4 prep, so how is
possible that your Cc list is so empty?



> +S:	Maintained
> +F:	arch/arm64/boot/dts/arm/morello*


Missing bindings.



Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: arm: Add Morello compatibility

[Vincenzo Frascino]

Hi Krzysztof,

Thank you for your review.

On 14/12/2024 10:08, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> Add compatibility to Arm Morello System Development Platform.
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>> index 8dd6b6446394..ea5a5e179ed1 100644
>> --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>> +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>> @@ -118,6 +118,9 @@ properties:
>>          items:
>>            - const: arm,foundation-aarch64
>>            - const: arm,vexpress
>> +      - description: Arm Morello System Development Platform
>> +        items:
>> +          - const: arm,morello
> 
> Why is this only SoC? Your commit msg is supposed to explain any
> oddities, because on first look that's just clearly wrong.
> 

Morello is at the same time the name of an Architecture and of an SoC.
I will add more information to the commit message in the next iteration.

Could you please provide more information of why you think it is clearly wrong?

> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties

[Vincenzo Frascino]

On 14/12/2024 10:10, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> Add support for "interrupt-names" and "mbox-name" optional properties.
> 
> Why?
> 
> 
> I wonder why you are not cc-ing other maintainers, like only Rob is
> acceptable by you?
>

No it is not. And this is why it is not a good idea to post patches on Friday
night. My intention was to copy linux-arm-kernel but I copied mistakenly
linux-kernel instead. I do apologize. I will fix this in the next iteration.

> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
> not CC people just because they made one commit years ago). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
> 
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
> </form letter>
> 
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Viresh Kumar <viresh.kumar@linaro.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  Documentation/devicetree/bindings/mailbox/arm,mhu.yaml | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
>> index d9a4f4a02d7c..65a4f66a7273 100644
>> --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
>> +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
>> @@ -63,6 +63,16 @@ properties:
>>        - description: high-priority non-secure
>>        - description: Secure
>>  
>> +  interrupt-names:
>> +    minItems: 2
>> +    items:
>> +      - const: mhu-lpri-rx
>> +      - const: mhu-hpri-rx
>> +      - const: mhu-si-rx
> 
> No, drop.
> 
>> +
>> +  mbox-name:
>> +    maxItems: 1
> 
> No clue what's this, for sure there is no such property at all and
> commit msg does not explain it.
> 
> 
> Drop entire patch.
>

Fine.

> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 1/8] dt-bindings: arm: Add Morello compatibility

[Krzysztof Kozlowski]

On 19/12/2024 16:07, Vincenzo Frascino wrote:
> Hi Krzysztof,
> 
> Thank you for your review.
> 
> On 14/12/2024 10:08, Krzysztof Kozlowski wrote:
>> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>>> Add compatibility to Arm Morello System Development Platform.
>>>
>>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>>> Cc: Rob Herring <robh@kernel.org>
>>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>> index 8dd6b6446394..ea5a5e179ed1 100644
>>> --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>> @@ -118,6 +118,9 @@ properties:
>>>          items:
>>>            - const: arm,foundation-aarch64
>>>            - const: arm,vexpress
>>> +      - description: Arm Morello System Development Platform
>>> +        items:
>>> +          - const: arm,morello
>>
>> Why is this only SoC? Your commit msg is supposed to explain any
>> oddities, because on first look that's just clearly wrong.
>>
> 
> Morello is at the same time the name of an Architecture and of an SoC.
> I will add more information to the commit message in the next iteration.
> 
> Could you please provide more information of why you think it is clearly wrong?

Because there is no board. Usually it is not possible to use SoC alone,
because pinout is too small to connect any wires...

Best regards,
Krzysztof

Re: [PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties

[Krzysztof Kozlowski]

On 19/12/2024 16:13, Vincenzo Frascino wrote:
> 
> 
> On 14/12/2024 10:10, Krzysztof Kozlowski wrote:
>> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>>> Add support for "interrupt-names" and "mbox-name" optional properties.
>>
>> Why?
>>
>>
>> I wonder why you are not cc-ing other maintainers, like only Rob is
>> acceptable by you?
>>
> 
> No it is not. And this is why it is not a good idea to post patches on Friday
> night. My intention was to copy linux-arm-kernel but I copied mistakenly
> linux-kernel instead. I do apologize. I will fix this in the next iteration.

It is not the problem here. Both lists should be. Just use tools instead
of selecting addresses.


Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: arm: Add Morello compatibility

[Vincenzo Frascino]

On 19/12/2024 15:25, Krzysztof Kozlowski wrote:
> On 19/12/2024 16:07, Vincenzo Frascino wrote:
>> Hi Krzysztof,
>>
>> Thank you for your review.
>>
>> On 14/12/2024 10:08, Krzysztof Kozlowski wrote:
>>> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>>>> Add compatibility to Arm Morello System Development Platform.
>>>>
>>>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>>>> Cc: Rob Herring <robh@kernel.org>
>>>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 3 +++
>>>>  1 file changed, 3 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>>> index 8dd6b6446394..ea5a5e179ed1 100644
>>>> --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>>> @@ -118,6 +118,9 @@ properties:
>>>>          items:
>>>>            - const: arm,foundation-aarch64
>>>>            - const: arm,vexpress
>>>> +      - description: Arm Morello System Development Platform
>>>> +        items:
>>>> +          - const: arm,morello
>>>
>>> Why is this only SoC? Your commit msg is supposed to explain any
>>> oddities, because on first look that's just clearly wrong.
>>>
>>
>> Morello is at the same time the name of an Architecture and of an SoC.
>> I will add more information to the commit message in the next iteration.
>>
>> Could you please provide more information of why you think it is clearly wrong?
> 
> Because there is no board. Usually it is not possible to use SoC alone,
> because pinout is too small to connect any wires...
> 

I like your attitude ;)

By the way there is a Morello Board as well. I will add it to the commit message
in the next iteration.

> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 2/8] dt-bindings: mailbox: arm,mhu: Add missing properties

[Vincenzo Frascino]

On 19/12/2024 15:26, Krzysztof Kozlowski wrote:
> On 19/12/2024 16:13, Vincenzo Frascino wrote:
>>
>>
>> On 14/12/2024 10:10, Krzysztof Kozlowski wrote:
>>> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>>>> Add support for "interrupt-names" and "mbox-name" optional properties.
>>>
>>> Why?
>>>
>>>
>>> I wonder why you are not cc-ing other maintainers, like only Rob is
>>> acceptable by you?
>>>
>>
>> No it is not. And this is why it is not a good idea to post patches on Friday
>> night. My intention was to copy linux-arm-kernel but I copied mistakenly
>> linux-kernel instead. I do apologize. I will fix this in the next iteration.
> 
> It is not the problem here. Both lists should be. Just use tools instead
> of selecting addresses.
>

Will do.

> 
> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 3/8] arm64: dts: morello: Add support for common functionalities

[Vincenzo Frascino]

On 14/12/2024 10:11, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
>> some functionalities that have conveniently been included in
>> morello.dtsi to avoid duplication.
>>
>> Introduce morello.dtsi.
>>
>> Note: Morello fvp will be introduced with a future patch series.
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  arch/arm64/boot/dts/arm/morello.dtsi | 112 +++++++++++++++++++++++++++
>>  1 file changed, 112 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
>> new file mode 100644
>> index 000000000000..9d84a0840c5b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/arm/morello.dtsi
>> @@ -0,0 +1,112 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
>> +/*
>> + * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	compatible = "arm,morello";
>> +
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	aliases {
>> +		serial0 = &soc_uart0;
>> +	};
>> +
>> +	gic: interrupt-controller@2c010000 {
>> +		compatible = "arm,gic-v3";
>> +		#address-cells = <2>;
>> +		#interrupt-cells = <3>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		interrupt-controller;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,armv8-pmuv3";
>> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +	};
>> +
>> +	spe-pmu {
>> +		compatible = "arm,statistical-profiling-extension-v1";
>> +		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2";
>> +		method = "smc";
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>> +	};
>> +
>> +	mailbox: mhu@45000000 {
> 
> 
> You cannot have MMIO nodes outside of soc.
> 

Ok, I will move it to morello.dtsi.

>> +		compatible = "arm,mhu-doorbell", "arm,primecell";
>> +		reg = <0x0 0x45000000 0x0 0x1000>;
>> +		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>> +			     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "mhu-lpri-rx",
>> +				  "mhu-hpri-rx";
>> +		#mbox-cells = <2>;
>> +		mbox-name = "ARM-MHU";
>> +		clocks = <&soc_refclk50mhz>;
>> +		clock-names = "apb_pclk";
>> +	};
>> +
>> +	sram: sram@45200000 {
>> +		compatible = "mmio-sram";
>> +		reg = <0x0 0x06000000 0x0 0x8000>;
>> +
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0x0 0x06000000 0x8000>;
>> +
>> +		cpu_scp_hpri0: scp-sram@0 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0x0 0x80>;
>> +		};
>> +
>> +		cpu_scp_hpri1: scp-sram@80 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0x80 0x80>;
>> +		};
>> +	};
>> +
>> +	soc_refclk50mhz: refclk50mhz {
> 
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> 

All right.

>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <50000000>;
>> +		clock-output-names = "apb_pclk";
>> +	};
>> +
>> +	soc_refclk85mhz: refclk85mhz {
> 
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> 
> 
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <85000000>;
>> +		clock-output-names = "iofpga:aclk";
>> +	};
>> +
>> +	soc_uartclk:  uartclk {
> 
> 
> Only one space.
> 
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> 
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <50000000>;
>> +		clock-output-names = "uartclk";
>> +	};
>> +
>> +	soc_uart0: serial@2a400000 {
>> +		compatible = "arm,pl011", "arm,primecell";
>> +		reg = <0x0 0x2a400000 0x0 0x1000>;
>> +		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
>> +		clock-names = "uartclk", "apb_pclk";
>> +		status = "okay";
> 
> Why do you need it? Did you disable it?
> 
>> +	};
>> +};
> 
> 
> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 4/8] arm64: dts: morello: Add support for soc dts

[Vincenzo Frascino]

On 14/12/2024 10:12, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> Introduce Morello SoC dts.
> 
> So Morello is an architecture, not a board or platform? You cannot have
> both...
> 
> 

So, Morello is an architecture an SoC and a platform.

To distinguish them I propose:
- arm,morello for # the SoC
- arm,morello-sdp # for the platform.

sdp: Software Development Platform.

> 
> 
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  arch/arm64/boot/dts/arm/morello-soc.dts | 267 ++++++++++++++++++++++++
>>  1 file changed, 267 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts
>>
>> diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts
>> new file mode 100644
>> index 000000000000..3c5247121e4d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/arm/morello-soc.dts
>> @@ -0,0 +1,267 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
>> +/*
>> + * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
>> +
>> + */
>> +
>> +/dts-v1/;
>> +#include "morello.dtsi"
>> +
>> +/ {
>> +	model = "Arm Morello System Development Platform";
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		secure-firmware@ff000000 {
>> +			reg = <0 0xff000000 0 0x01000000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +		cpu0: cpu0@0 {
>> +			compatible = "arm,neoverse-n1";
>> +			reg = <0x0 0x0>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			clocks = <&scmi_dvfs 0>;
>> +		};
>> +		cpu1: cpu1@100 {
>> +			compatible = "arm,neoverse-n1";
>> +			reg = <0x0 0x100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			clocks = <&scmi_dvfs 0>;
>> +		};
>> +		cpu2: cpu2@10000 {
>> +			compatible = "arm,neoverse-n1";
>> +			reg = <0x0 0x10000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			clocks = <&scmi_dvfs 1>;
>> +		};
>> +		cpu3: cpu3@10100 {
>> +			compatible = "arm,neoverse-n1";
>> +			reg = <0x0 0x10100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			clocks = <&scmi_dvfs 1>;
>> +		};
>> +	};
>> +
>> +	/* The first bank of memory, memory map is actually provided by UEFI. */
>> +	memory@80000000 {
>> +		device_type = "memory";
>> +		/* [0x80000000-0xffffffff] */
>> +		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
>> +	};
>> +
>> +	memory@8080000000 {
>> +		device_type = "memory";
>> +		/* [0x8080000000-0x83f7ffffff] */
>> +		reg = <0x00000080 0x80000000 0x3 0x78000000>;
>> +	};
>> +
>> +	smmu_pcie: iommu@4f400000 {
> 
> This all is weird. MMIO nodes outside of soc, soc pieces defined in DTS
> instead of DTSI.
> 
> Please look first how all other DTS and DTSI are done. Also carefully
> read DTS coding style.
> 
>

All right, will do.


> 
> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 5/8] arm64: Introduce Arm Morello System Development Platform

[Vincenzo Frascino]

On 14/12/2024 10:13, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> Introduce the Kconfig entry for the Arm Morello System Development
>> Platform.
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  arch/arm64/Kconfig.platforms | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 370a9d2b6919..1c4867ea9407 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -250,6 +250,11 @@ config ARCH_NPCM
>>  	  General support for NPCM8xx BMC (Arbel).
>>  	  Nuvoton NPCM8xx BMC based on the Cortex A35.
>>  
>> +config ARCH_MORELLO
>> +	bool "Arm Morello System Development Platform"
>> +	help
>> +	  Enables support for Arm Morello System Development Platform
> 
> You do not get new ARCH per each soc or product. Merge it to existing
> ARM Kconfigs.
> 

Thanks, this is the feedback I was looking for.

> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 6/8] arm64: dts: Add Arm Morello System Development Platform support

[Vincenzo Frascino]

On 14/12/2024 10:14, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> Introduce Arm Morello System Development Platform support.
>>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  arch/arm64/boot/dts/arm/Makefile | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
>> index d908e96d7ddc..0a821808692e 100644
>> --- a/arch/arm64/boot/dts/arm/Makefile
>> +++ b/arch/arm64/boot/dts/arm/Makefile
>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
>>  dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
>>  dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
>>  dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
>> +dtb-$(CONFIG_ARCH_MORELLO) += morello-soc.dtb
> 
> No, you organize patches in insane way. Makefile is never, never
> separate entry.
> 
> Look how all existing submissions were done.
> 
> Squash the patches.
> 

Generally in v1 I tend to make evident things on which I want comments to make
sure they are not missed.

Here and in the previous patch I wanted to know if ARCH_MORELLO could live as a
separate entity.

Now that you replied, it will be squashed where it belongs in v2.

> You also did not CC several people and at least arm kernel list. Use
> standard tools for development instead of inventing your own process.
> 
> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
> not CC people just because they made one commit years ago). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
> 
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
> </form letter>
> 
> 
> 
> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Vincenzo Frascino]

On 14/12/2024 10:19, Krzysztof Kozlowski wrote:
> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  MAINTAINERS | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index e6e71b05710b..8199e5945fb2 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3304,6 +3304,12 @@ F:	drivers/clocksource/timer-versatile.c
>>  X:	drivers/cpufreq/vexpress-spc-cpufreq.c
>>  X:	Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>  
>> +ARM MORELLO PLATFORM SUPPORT
> 
> Wrongly placed, M is not after V, I know people cannot keep order but
> let's try. No need for new Boogaloo.
> 
> Plus look how all the titles are created and do not come with different
> style.
> 

Not sure I understand what you mean here. Do you mean that I have to put Morello
in alphabetical order in the file? Or just above VEXPRESS?

For what concerns the title, the MAINTAINERS file contains several styles (...
PLATFORM, PLATFORM SUPPORT, etc). What's your preference?

>> +M:	Vincenzo Frascino <vincenzo.frascino@arm.com>
>> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> 
> 
> So why you did not bother to Cc this list? You are supposed to develop
> on mainline kernel and then run get_maintainers.pl or b4 prep, so how is
> possible that your Cc list is so empty?
> 
> 
> 
>> +S:	Maintained
>> +F:	arch/arm64/boot/dts/arm/morello*
> 
> 
> Missing bindings.
> 
> 

There are no bindings specific to morello. What should I add here?

> 
> Best regards,
> Krzysztof

-- 
Regards,
Vincenzo

Re: [PATCH 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Krzysztof Kozlowski]

On 19/12/2024 18:45, Vincenzo Frascino wrote:
> 
> 
> On 14/12/2024 10:19, Krzysztof Kozlowski wrote:
>> On 13/12/2024 17:32, Vincenzo Frascino wrote:
>>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>>> Cc: Rob Herring <robh@kernel.org>
>>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>> ---
>>>  MAINTAINERS | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index e6e71b05710b..8199e5945fb2 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -3304,6 +3304,12 @@ F:	drivers/clocksource/timer-versatile.c
>>>  X:	drivers/cpufreq/vexpress-spc-cpufreq.c
>>>  X:	Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
>>>  
>>> +ARM MORELLO PLATFORM SUPPORT
>>
>> Wrongly placed, M is not after V, I know people cannot keep order but
>> let's try. No need for new Boogaloo.
>>
>> Plus look how all the titles are created and do not come with different
>> style.
>>
> 
> Not sure I understand what you mean here. Do you mean that I have to put Morello
> in alphabetical order in the file? Or just above VEXPRESS?

Entries in maintainers are ordered, keep the order.

> 
> For what concerns the title, the MAINTAINERS file contains several styles (...
> PLATFORM, PLATFORM SUPPORT, etc). What's your preference?

Look how other arm platforms are called, e.g. vexpress. Create the same
style.


>>
>>
>> Missing bindings.
>>
>>
> 
> There are no bindings specific to morello. What should I add here?
> 

Ah, indeed, you added these to Vexpress Juno bindings. I missed that.
It's fine then.

Best regards,
Krzysztof