From: Jarkko Nikula <jarkko.nikula@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Michael Wu <michael.wu@kneron.us>
Cc: Andi Shyti <andi.shyti@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Jan Dabros <jsd@semihalf.com>,
linux-i2c@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Morgan Chang <morgan.chang@kneron.us>,
mvp.kutali@gmail.com
Subject: Re: [PATCH v4 2/2] i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters
Date: Thu, 3 Oct 2024 16:25:23 +0300 [thread overview]
Message-ID: <727b4614-5010-4ae5-8890-11b12c362048@linux.intel.com> (raw)
In-Reply-To: <Zv6C8Zj4NabZf_PM@smile.fi.intel.com>
On 10/3/24 2:41 PM, Andy Shevchenko wrote:
> On Thu, Oct 03, 2024 at 07:15:24PM +0800, Michael Wu wrote:
>> In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameter
>> for High Speed Mode") the SCL high period count and low period count for
>> high speed mode are calculated based on fixed tHIGH = 160 and tLOW = 120.
>> However, the set of two fixed values is only applicable to the combination
>> of hardware parameters IC_CAP_LOADING is 400 and IC_CLK_FREQ_OPTIMIZATION
>> is true. Outside of this combination, the SCL frequency may not reach
>> 3.4 MHz because the fixed tHIGH and tLOW are not small enough.
>>
>> If IC_CAP_LOADING is 400, it means the bus capacitance is 400pF;
>> Otherwise, 100 pF. If IC_CLK_FREQ_OPTIMIZATION is true, it means that the
>> hardware reduces its internal clock frequency by reducing the internal
>> latency required to generate the high period and low period of the SCL line.
>>
>> Section 3.15.4.5 in DesignWare DW_apb_i2b Databook v2.03 says that when
>> IC_CLK_FREQ_OPTIMIZATION = 0,
>>
>> MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
>> = 120 ns for 3.4 Mbps, bus loading = 400pF
>> MIN_SCL_LOWtime = 160 ns for 3.4 Mbps, bus loading = 100pF
>> = 320 ns for 3.4 Mbps, bus loading = 400pF
>>
>> and section 3.15.4.6 says that when IC_CLK_FREQ_OPTIMIZATION = 1,
>>
>> MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
>> = 160 ns for 3.4 Mbps, bus loading = 400pF
>> MIN_SCL_LOWtime = 120 ns for 3.4 Mbps, bus loading = 100pF
>> = 320 ns for 3.4 Mbps, bus loading = 400pF
>>
>> In order to calculate more accurate SCL high period count and low period
>> count for high speed mode, two hardware parameters IC_CAP_LOADING and
>> IC_CLK_FREQ_OPTIMIZATION must be considered together. Since there're no
>> registers controlliing these these two hardware parameters, users can
>> declare them in the device tree so that the driver can obtain them.
>
> As long as DT schema (new properties) is accepted, this LGTM now,
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
next prev parent reply other threads:[~2024-10-03 13:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-03 11:15 [PATCH v4 0/2] Compute HS HCNT and LCNT based on HW parameters Michael Wu
2024-10-03 11:15 ` [PATCH v4 1/2] dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk freq optimized Michael Wu
2024-10-03 13:21 ` Krzysztof Kozlowski
2024-10-03 11:15 ` [PATCH v4 2/2] i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters Michael Wu
2024-10-03 11:41 ` Andy Shevchenko
2024-10-03 13:25 ` Jarkko Nikula [this message]
2024-10-28 5:24 ` [PATCH v4 0/2] Compute HS HCNT and LCNT " Michael Wu
2024-11-19 22:58 ` Andi Shyti
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