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Fri, 17 Apr 2026 08:20:56 -0700 (PDT) X-Received: by 2002:a17:902:8b87:b0:2b0:a980:367c with SMTP id d9443c01a7336-2b5f9eb0513mr25693395ad.2.1776439255583; Fri, 17 Apr 2026 08:20:55 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab20c4fsm31121345ad.59.2026.04.17.08.20.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Apr 2026 08:20:55 -0700 (PDT) Message-ID: <72badc70-8a49-1bf6-291b-1dcf245b8991@oss.qualcomm.com> Date: Fri, 17 Apr 2026 20:50:46 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH 05/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux To: Mukesh Ojha Cc: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> <20260414-glymur-v1-5-7d3d1cf57b16@oss.qualcomm.com> <20260414063128.6ass64wfi7nmtzti@hu-mojha-hyd.qualcomm.com> Content-Language: en-US In-Reply-To: <20260414063128.6ass64wfi7nmtzti@hu-mojha-hyd.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Kd7idwYD c=1 sm=1 tr=0 ts=69e24fd9 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=tkXzD9pcQE_IdLLthRAA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: WP-1_z6hyOj8jVne-arPjGrHyf1JYumU X-Proofpoint-ORIG-GUID: WP-1_z6hyOj8jVne-arPjGrHyf1JYumU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDE1NSBTYWx0ZWRfX9luxof8AepM8 jWQWNBR6+2Z4nxpoo5i65vTF/Q5UfYG6KtLME8iAtjmjyqscwC3MT6K7+1aE/YIHy4fxkKn2ym8 lIVizwjh3WQ/8pprmkYSVROgvsH84Up3vDRw1jy2FOcanKeDYjU0t1IVsjGazXrAJvFlQfiMFG2 TWg79t7S4pZ9Vr9ER1NlSYxOzu4dvAbgY6YMOIo+edvkbz44xsmwYDjJyFE7eyx4EbPm/FhxUGS NnTIyLCml11yGC5Wu+YMzh8VBGOfYmsH5mYxiOYT4Rtr3RId7RltRpje+lFHNd7St+YxhHRuPYh GeTVsRe9ERBnCAHjW83cdnVx/Ujd4eyOHbQlmCBSW8/NDnbcGSXRB8h6wX74QPrJJuSDfkhIqek rMT4+66JjCI7MDw1DVCMH6Y/D/V5hftmkyNqv+2BXVuYVRcFWPReBByr88ujONVjO8TaNSMwOOK pxCsk8zesP3MzRtCOZw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170155 On 4/14/2026 12:01 PM, Mukesh Ojha wrote: > On Tue, Apr 14, 2026 at 10:30:01AM +0530, Vishnu Reddy wrote: >> From: Mukesh Ojha >> >> Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah >> or QHEE), which typically handles IOMMU configuration. This includes >> mapping memory regions and device memory resources for remote processors >> by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are >> later removed during teardown. Additionally, SHM bridge setup is required >> to enable memory protection for both remoteproc metadata and its memory >> regions. >> >> When the hypervisor is absent, the operating system must perform these >> configurations instead. >> >> Support for handling IOMMU and SHM setup in the absence of a hypervisor >> is now in place. Extend the Iris driver to enable this functionality on >> platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). >> >> Additionally, the Iris driver must map the firmware and its required >> resources to the firmware SID, which is now specified via iommu-map in >> the device tree. >> >> Co-developed-by: Vikash Garodia >> Signed-off-by: Vikash Garodia >> Signed-off-by: Mukesh Ojha >> Signed-off-by: Vishnu Reddy >> --- >> drivers/media/platform/qcom/iris/iris_core.h | 4 ++ >> drivers/media/platform/qcom/iris/iris_firmware.c | 71 +++++++++++++++++++++--- >> 2 files changed, 66 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h >> index fb194c967ad4..aa7abef6f0e0 100644 >> --- a/drivers/media/platform/qcom/iris/iris_core.h >> +++ b/drivers/media/platform/qcom/iris/iris_core.h >> @@ -34,6 +34,8 @@ enum domain_type { >> * struct iris_core - holds core parameters valid for all instances >> * >> * @dev: reference to device structure >> + * @dev_fw: reference to the context bank device used for firmware load >> + * @ctx_fw: SCM PAS context for authenticated firmware load and shutdown >> * @reg_base: IO memory base address >> * @irq: iris irq >> * @v4l2_dev: a holder for v4l2 device structure >> @@ -77,6 +79,8 @@ enum domain_type { >> >> struct iris_core { >> struct device *dev; >> + struct device *dev_fw; >> + struct qcom_scm_pas_context *ctx_fw; > fw_dev suits better and ctx_fw is always for firmware, maybe pas_ctx is > better. Ack >> void __iomem *reg_base; >> int irq; >> struct v4l2_device v4l2_dev; >> diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c >> index 5f408024e967..93d77996c83f 100644 >> --- a/drivers/media/platform/qcom/iris/iris_firmware.c >> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c >> @@ -5,6 +5,7 @@ >> >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -13,12 +14,15 @@ >> #include "iris_firmware.h" >> >> #define MAX_FIRMWARE_NAME_SIZE 128 >> +#define IRIS_FW_START_ADDR 0 >> >> static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> { >> + struct device *dev = core->dev_fw ? core->dev_fw : core->dev; >> u32 pas_id = core->iris_platform_data->pas_id; >> const struct firmware *firmware = NULL; >> - struct device *dev = core->dev; >> + struct qcom_scm_pas_context *ctx_fw; >> + struct iommu_domain *domain; >> struct resource res; >> phys_addr_t mem_phys; >> size_t res_size; >> @@ -29,13 +33,17 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4) >> return -EINVAL; >> >> - ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); >> + ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res); >> if (ret) >> return ret; >> >> mem_phys = res.start; >> res_size = resource_size(&res); >> >> + ctx_fw = devm_qcom_scm_pas_context_alloc(dev, pas_id, mem_phys, res_size); >> + if (IS_ERR(ctx_fw)) >> + return PTR_ERR(ctx_fw); >> + >> ret = request_firmware(&firmware, fw_name, dev); >> if (ret) >> return ret; >> @@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> goto err_release_fw; >> } >> >> - ret = qcom_mdt_load(dev, firmware, fw_name, >> - pas_id, mem_virt, mem_phys, res_size, NULL); >> + ctx_fw->use_tzmem = !!core->dev_fw; >> + ret = qcom_mdt_pas_load(ctx_fw, firmware, fw_name, mem_virt, NULL); >> + if (ret) >> + goto err_mem_unmap; >> + >> + if (ctx_fw->use_tzmem) { >> + domain = iommu_get_domain_for_dev(core->dev_fw); >> + if (!domain) { >> + ret = -ENODEV; >> + goto err_mem_unmap; >> + } >> + >> + ret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size, >> + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); >> + if (ret) >> + goto err_mem_unmap; >> + } >> >> + core->ctx_fw = ctx_fw; >> + >> +err_mem_unmap: >> memunmap(mem_virt); >> err_release_fw: >> release_firmware(firmware); >> @@ -62,6 +88,19 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> return ret; >> } >> >> +static void iris_fw_iommu_unmap(struct iris_core *core) >> +{ >> + bool use_tzmem = core->ctx_fw->use_tzmem; >> + struct iommu_domain *domain; >> + >> + if (!use_tzmem) >> + return; >> + >> + domain = iommu_get_domain_for_dev(core->dev_fw); >> + if (domain) >> + iommu_unmap(domain, IRIS_FW_START_ADDR, core->ctx_fw->mem_size); >> +} >> + >> int iris_fw_load(struct iris_core *core) >> { >> const struct tz_cp_config *cp_config; >> @@ -79,10 +118,10 @@ int iris_fw_load(struct iris_core *core) >> return -ENOMEM; >> } >> >> - ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); >> + ret = qcom_scm_pas_prepare_and_auth_reset(core->ctx_fw); >> if (ret) { >> dev_err(core->dev, "auth and reset failed: %d\n", ret); >> - return ret; >> + goto err_unmap; >> } >> >> for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { >> @@ -93,17 +132,31 @@ int iris_fw_load(struct iris_core *core) >> cp_config->cp_nonpixel_size); >> if (ret) { >> dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); >> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); >> - return ret; >> + goto err_pas_shutdown; >> } >> } >> >> + return 0; >> + >> +err_pas_shutdown: >> + qcom_scm_pas_shutdown(core->ctx_fw->pas_id); >> +err_unmap: >> + iris_fw_iommu_unmap(core); >> + >> return ret; >> } >> >> int iris_fw_unload(struct iris_core *core) >> { >> - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); >> + int ret; >> + >> + ret = qcom_scm_pas_shutdown(core->ctx_fw->pas_id); >> + if (ret) >> + return ret; >> + >> + iris_fw_iommu_unmap(core); >> + >> + return ret; >> } >> >> int iris_set_hw_state(struct iris_core *core, bool resume) >> >> -- >> 2.34.1 >>