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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f25915785sm15777430f8f.58.2025.02.18.07.41.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Feb 2025 07:41:06 -0800 (PST) Message-ID: <72c01aae-33d1-45f8-94ce-b0fcfe4fec00@nexus-software.ie> Date: Tue, 18 Feb 2025 15:41:05 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: dts: qcom: Add MXC power domain to videocc nodes To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> <20250218-videocc-pll-multi-pd-voting-v1-5-cfe6289ea29b@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250218-videocc-pll-multi-pd-voting-v1-5-cfe6289ea29b@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 18/02/2025 14:26, Jagadeesh Kona wrote: > Videocc requires both MMCX and MXC rails to be powered ON > to configure the video PLLs on SM8450, SM8550 and SM8650 > platforms. Hence add MXC power domain to videocc node on > these platforms. > > Signed-off-by: Jagadeesh Kona > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- > 3 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 9c809fc5fa45a98ff5441a0b6809931588897243..4f8dca8fc64212191780067c5d8815e3a2bb137f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -3136,7 +3136,8 @@ videocc: clock-controller@aaf0000 { > reg = <0 0x0aaf0000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > required-opps = <&rpmhpd_opp_low_svs>; > #clock-cells = <1>; > #reset-cells = <1>; > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index eac8de4005d82f246bc50f64f09515631d895c99..a039ae71e1b7bba8124128d19de5e00c65217770 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2889,7 +2889,8 @@ videocc: clock-controller@aaf0000 { > reg = <0 0x0aaf0000 0 0x10000>; > clocks = <&bi_tcxo_div2>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > required-opps = <&rpmhpd_opp_low_svs>; > #clock-cells = <1>; > #reset-cells = <1>; > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..32af2a0f7a0030f155b7d8c93faeffa384a42768 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -3524,7 +3524,8 @@ videocc: clock-controller@aaf0000 { > reg = <0 0x0aaf0000 0 0x10000>; > clocks = <&bi_tcxo_div2>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > Reviewed-by: Bryan O'Donoghue