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[46.193.119.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488982e3244sm14946025e9.12.2026.04.03.01.28.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Apr 2026 01:28:09 -0700 (PDT) Message-ID: <72c9a165-74bb-42a5-b5fe-67bfa2c8ce2e@gmail.com> Date: Fri, 3 Apr 2026 10:28:08 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: dsa: microchip: add KSZ low-loss cable errata properties To: Andrew Lunn Cc: Woojung Huh , UNGLinuxDriver@microchip.com, Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , Maxime Chevallier , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fidelio Lawson References: <20260326-ksz87xx_errata_low_loss_connections-v1-0-79a698f43626@exotec.com> <20260326-ksz87xx_errata_low_loss_connections-v1-1-79a698f43626@exotec.com> <521cf729-50d2-44c1-8c96-c1fba2127b9d@lunn.ch> Content-Language: en-US From: Fidelio LAWSON In-Reply-To: <521cf729-50d2-44c1-8c96-c1fba2127b9d@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 3/26/26 13:14, Andrew Lunn wrote: > On Thu, Mar 26, 2026 at 10:10:21AM +0100, Fidelio Lawson wrote: >> Microchip KSZ87xx switches are affected by the "Module 3: Equalizer fix >> for short cables" erratum described in DS80000687C. >> The embedded PHY receivers are tuned for long, high-loss cables, >> which may cause signal distortion when operated with short or low-loss >> cabling such as CAT5e or CAT6. In these cases, >> the PHY may fail to establish a link due to internal over-amplification. >> >> Two workarounds are provided by Microchip, each configuring a different >> indirect register value to adjust the PHY equalizer settings. >> >> This patch introduces two new device tree properties to enable and >> select the appropriate workaround: >> >> - microchip,low-loss-errata-enable: boolean enabling the feature >> - microchip,low-loss-errata: selects workaround 1 or 2 (default: 1) >> >> These properties allow board designers to opt into the errata fix >> according to the targeted cable characteristics of their platform. > > Does the errata give any indication how the two different workarounds > differ? How would a user decided which to use? > > I also question if this should be a DT property. The length of the > cables is not a property of the board. > > A PHY tunable would better reflect the same board can be used with > different cables, with different lengths/quality. > > Andrew Hi Andrew, Thanks for the review. Regarding the difference between the two workarounds: Microchip’s errata does provide some insight into how they behave and when each should be used. Workaround 1 modifies the PHY equalizer settings by adjusting an indirect register (0x3c). According to Microchip’s support article: “The above register change makes the equalizer’s compensation range wider, and therefore cables with various characteristics can be tolerated. Adjust equalizer EQ training algorithm to cover a few type of short cables issue. Also is appropriate for board‑to‑board connection and port‑to‑port connection with the capacitor AC coupling mode.” Microchip also explains that although the default value in register 0x3c handles standard short Ethernet cables (CAT‑5/CAT‑5e), a more optimized value (0x15) provides better tolerance for corner cases, especially very short or board‑to‑board links: “Based on tests, a more optimized equalizer adjustment value 0x15 is better for all corner cases of the short cable and short distance connection for port‑to‑port or board‑to‑board cases.” So Workaround 1 primarily widens and optimizes the DSP equalizer EQ compensation range, and is expected to solve most short/low‑loss cable issues. Workaround 2 is intended for the cases where Workaround 1 is not sufficient. This one adjusts the receiver low‑pass filter bandwidth, effectively reducing the high‑frequency component of the received signal: “Based on the root cause above, adjust the receiver low pass filter to reduce the high frequency component to keep the receive signal within a reasonable range when using CAT‑5E and CAT‑6 cable.” So Workaround 2 is a more aggressive filtering approach, applied only when the EQ adjustment alone does not stabilize the link on CAT‑5e/CAT‑6 short cable scenarios. Regarding the question of whether this should be exposed through a PHY tunable: I understand your concern. The erratum is indeed linked to cable characteristics, not the board itself. Since this patch modifies registers that belong to the DSA switch itself, and not the PHY driver, I’m not entirely sure it would be architecturally correct to expose these adjustments as PHY tunables. The workarounds target internal receiver/equalizer settings inside the KSZ87xx switch block, accessed via the switch’s indirect register mechanism, not via a standard phy_device. Given that, I’m unsure whether mapping these switch‑level registers into the PHY tunables framework would be appropriate or even feasible. What do you think? Best regards, Fidelio